AAT1142
800mA Voltage-Scaling Step-Down Converter
Since RDS(ON), quiescent current, and switching
2. C1 and L1 should be connected as closely as
possible. The connection of L1 to the LX pin
(Pin 1) should be as short as possible.
losses all vary with input voltage, the total losses
should be investigated over the complete input
voltage range.
3. The feedback pin (Pin 7) should be separate
from any power trace and connected close to the
VOUT terminal. Sensing along a high-current
load trace will degrade VOUT load regulation.
4. The resistance of the trace from the GND ter-
minal to PGND (Pin 2) should be kept to a min-
imum. This will help to minimize any error in DC
regulation due to differences in the potential of
the internal signal ground and the power
ground.
5. Connect unused signal pins to ground to avoid
unwanted noise coupling. When using S2Cwire,
connect SDA and SCL to ground to disable I2C
functionality.
6. When using the TDFN33-12 package, connect
the exposed paddle (EP) to the GND plane.
Given the total losses, the maximum junction tem-
perature can be derived from the θJA for the
TSOPJW-12 package which is 160°C/W.
TJ(MAX)
=
PTOTAL
·
Θ
JA + TAMB
Layout
The suggested PCB layout for the AAT1142 in a
TSOPJW-12 package is shown in Figures 7 and 8.
The following guidelines should be used to help
ensure a proper layout.
1. The input capacitor (C2) should connect as
closely as possible to VIN (Pin 12) and PGND
(Pin 2).
Figure 7: AAT1142 Evaluation Board
Figure 8: AAT1142 Evaluation Board
Top Side Layout (TSOPJW-12 Package).
Bottom Side Layout (TSOPJW-12 Package).
1142.2006.07.1.0
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