AAT1142
800mA Voltage-Scaling Step-Down Converter
capacitors are ideal for this function. To minimize
current demand. The relationship of the output volt-
age droop during the three switching cycles to the
output capacitance can be estimated by:
stray inductance, the capacitor should be placed as
closely as possible to the IC. This keeps the high
frequency content of the input current localized,
minimizing EMI and input voltage ripple.
3
·
VDROOP FS
ΔILOAD
COUT
=
Proper placement of the input capacitor (C1) is
shown in the evaluation board layout in Figure 7.
·
A laboratory test set-up typically consists of two
long wires running from the bench power supply to
the evaluation board input voltage pins. The induc-
tance of these wires, along with the low-ESR
ceramic input capacitor, can create a high Q net-
work that may affect converter performance. This
problem often becomes apparent in the form of
excessive ringing in the output voltage during load
transients. Errors in the loop phase and gain meas-
urements can also result.
Once the average inductor current increases to the
DC load level, the output voltage recovers. The
above equation establishes a limit on the minimum
value for the output capacitor with respect to load
transients.
The internal voltage loop compensation also limits
the minimum output capacitor value to 4.7μF. This
is due to its effect on the loop crossover frequency
(bandwidth), phase margin, and gain margin.
Increased output capacitance will reduce the
crossover frequency with greater phase margin.
Since the inductance of a short PCB trace feeding
the input voltage is significantly lower than the
power leads from the bench power supply, most
applications do not exhibit this problem.
Thermal Calculations
There are three types of losses associated with the
AAT1142 step-down converter: switching losses,
conduction losses, and quiescent current losses.
Conduction losses are associated with the RDS(ON)
characteristics of the power output switching
devices. Switching losses are dominated by the gate
charge of the power output switching devices. At full
load, assuming continuous conduction mode
(CCM), a simplified form of the losses is given by:
In applications where the input power source lead
inductance cannot be reduced to a level that does
not affect the converter performance, a high ESR
tantalum or aluminum electrolytic capacitor should
be placed in parallel with the low ESR, ESL bypass
ceramic capacitor. This dampens the high Q net-
work and stabilizes the system.
Output Capacitor
The output capacitor limits the output ripple and
provides holdup during large load transitions. A
4.7µF to 10µF X5R or X7R ceramic capacitor typi-
cally provides sufficient bulk capacitance to stabilize
the output during large load transitions and has the
ESR and ESL characteristics necessary for low out-
put ripple. A smaller capacitor may result in slightly
increased no load output regulation and output rip-
ple with input voltages above 5V. This should be
verified under actual operating conditions.
IO2 · (RDS(ON)H · VO + RDS(ON)L · [VIN - VO])
PTOTAL
=
VIN
+ (tsw · FS · IO + IQ) · VIN
IQ is the step-down converter quiescent current.
The term tsw is used to estimate the full load step-
down converter switching losses.
The output voltage droop due to a load transient is
dominated by the capacitance of the ceramic out-
put capacitor. During a step increase in load cur-
rent, the ceramic output capacitor alone supplies
the load current until the loop responds. Within two
or three switching cycles, the loop responds and
the inductor current increases to match the load
For the condition where the step-down converter is
in dropout at 100% duty cycle, the total device dis-
sipation reduces to:
PTOTAL = IO2 · RDS(ON)H + IQ · VIN
18
1142.2006.07.1.0
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