ATA01501
Indirect Measurement of Optical Overload
1.9
Optical overload can be defined as the maximum
1.85
1.8
optical power above which the BER (bit error rate)
10
increases beyond 1 error in 10
bits. The
1.75
1.7
VDD = 5.5 V
ATA00501D1C is 100% tested at die sort by a DC
measurement which has excellent correlation with
an PRBS optical overload measurement. The mea-
surement consists of sinking a negative current
VDD =
5.0V
1.65
1.6
(see V
vs I figure) from the TIA and determin-
OUT
IN
ing the point of output voltage collapse. Also the
input node virtual ground during heavy AGC is
checked to verify that the linearity (i.e. pulse width
distortion) of the amplifier has not been compro-
mised.
1.55
1.5
VDD =
4.5V
- 40
10
Temperature oC
60
Measurement of Input Referred Noise
Current
The Input Noise Current is directly related to
sensitivity . It can be defined as the output noise
voltage (Vout), with no input signal, (including a 30
MHz lowpass filter at the output of the TIA) divided by
the AC transresistance.
Figure 11: Input Offset Voltage vs. Temperature
CBY Connection
The C
pad must be connected via a low
BY
inductance path to a surface mount capacitor of at
least 56pF (additional capacitance can be added in
parallel with the 56 pF or 220 pF capacitors to
improve low frequency response and noise
performance). Referring to the equivalent circuit
diagram and the typical bonding diagram, it is critical
that the connection from CBY to the bypass capacitor
use two bond wires for low inductance, since any
high frequency impedance at this node will be fed
back to the open loop amplifier with a resulting loss
of transimpedance bandwidth. Two pads are
provided for this purpose
14
Rf
10
CT
50
6
CT=1.0pF
2
CT =0.5pF
100 1000
- 0.1
1
10
Frequency (MHz)
Figure 12: Input Referred Noise Spectral Density
Sensitivity and Bandwidth
In order to guarantee sensitivity and bandwidth
Input Referred Noise Test Circuit
16
performance, the TIA is subjected to
a
comprehensive series of tests at the die sort level
VDD = 4.5V
25dB
o
(100% testing at 25 C) to verify the DC parametric
15
100
performance and the high frequency performance
(i.e. adequate |S21|) of the amplifier. Acceptably high
|S21| of the internal gain stages will ensure low
amplifier input capacitance and hence low input
referred noise current. Transimpedance sensitivity
and bandwidth are then guaranteed by design and
correlation with RF and DC die sort test results.
MHz
TIA
0.5pF
14
LPF
13
VDD=5.5V
12
6500in
R
η(dBm)=10LOG
11
- 40
0
40
80
Temperature (oC)
FIgure 13: Input Referred Noise vs Temperature
PRELIMINARY DATA SHEET - Rev 1.6
08/2001
7
ANADIGICS [ ANADIGICS, INC ]
