ATA01501
VDD
VDD
0.1µF
56pF
VDD
56pF
NC
12
GND
11
10
VDD2
GND
GND
1992
VOUT
NC
1
2
NC
9
19 I
PIN
IIN
8
0.1µF
Vout
GND
OUT
IIN
7
3
BY
BY
C
GND
GND
C
GND
CAGC GND
GND
GND
or
4
5
6
56pF
56pF
Neg.Supply
56 pF
56 pF
Figure 4:ATA01501D1C Die Typical Bonding
Figure 5: ATA01501DS2C Typical SQFP
Connection Package
Power Supplies and General Layout
CT = 0.5 pF
0.17
The ATA00501D1C may be operated from a positive
supply as low as +4.5 V and as high as +6.0 V. Below
+4.5 V, bandwidth, overload and sensitivity will
degrade, while at +6.0 V, bandwidth, overload and
sensitivity improve (see Bandwidth vs. Temperature
curves). Use of surface mount (preferably MIM type
capacitors), low inductance power supply bypass
capacitors (>=56pF) are essential for good high
frequency and low noise performance. The power
supply bypass capacitors should be mounted on or
connected to a good low inductance ground plane.
VDD
=
5.5 V
0.15
0.13
0.11
VDD
=
5.0 V
VDD = 4.5 V
0.90
General Layout Considerations
-40
10
60
85
Since the gain stages of the transimpedance
amplifier have an open loop bandwidth in excess
of 1.0 GHz, it is essential to maintain good high
frequency layout practices. To prevent oscillations,
a low inductance RF ground plane should be made
available for power supply bypassing. Traces that
can be made short should be made short, and
the utmost care should be taken to maintain very
low capacitance at the photodiode-TIA interface
Temperature (O C)
Figure 6: Bandwidth vs. Temperature
(I ), as excess capacitance at this node will
IN
cause a degradation in bandwidth and sensitivity
(see Bandwidth vs. C curves).
T
PRELIMINARY DATA SHEET - Rev 1.6
08/2001
5
ANADIGICS [ ANADIGICS, INC ]
