AS29LV800
March 2001
®
AC test conditions
+3.0V
1N3064
or equivalent
2.7KΩ
Device under test
6.2KΩ
CL*
1N3064
or equivalent
VSS
VSS
VSS
Test specifications
Test Condition
-70R,-80
-90, -120
1 TTL gate
100
Unit
Output Load
Output Load Capacitance CL (including jig capacitance)
Input Rise and Fall Times
30
pF
ns
V
5
Input Pulse Levels
0.0-3.0
1.5
Input timing measurement reference levels
Output timing measurement reference levels
V
1.5
V
Erase and programming performance
Limits
Parameter
Min
Typical
Max
15
Unit
sec
Sector erase and verify-1 time (excludes 00h programming
prior to erase)
-
1.0
Byte
-
-
-
-
10
15
300
360
27
-
µs
µs
Programming time
Word
Chip programming time
Erase/program cycles*
7.2
sec
100,000
cycles
* Erase/program cycle test is not verified on each shipped unit.
Latchup tolerance
Parameter
Min
-1.0
-0.5
-100
Max
+12.0
Unit
V
Input voltage with respect to VSS on A9, OE, and RESET pin
Input voltage with respect to VSS on all DQ, address, and control pins
VCC+0.5
+100
V
Current
mA
Includes all pins except VCC. Test conditions: VCC = 3.0V, one pin at a time.
3/22/01; V.1.0
Alliance Semiconductor
P. 22 of 25
ANADIGICS [ ANADIGICS, INC ]
