AIT1042
LSB
Table 17: Complete Register Map
MSB
PLL2_Ref (Downconverter Reference Divider Register)
Firstꢀdataꢀbyte
Secondꢀdataꢀbyte
Thirdꢀdataꢀbyte
23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
1
0
0
1
0
0
0
Rꢀcounter
PLL2_Main (Downconverter Main Divider Register)
Firstꢀdataꢀbyte
Secondꢀdataꢀbyte
Thirdꢀdataꢀbyte
23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
0
1
0
0
0
0
Bꢀcounter
Aꢀcounter
PLL1_Ref (Upconverter Reference Divider Register)
Firstꢀdataꢀbyte
Secondꢀdataꢀbyte
Thirdꢀdataꢀbyte
23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
1
0
0
0
0
0
1
0
0
1
0
0
0
0
0
Rꢀcounter
PLL1_Main (Upconverter Main Divider Register)
Firstꢀdataꢀbyte
Secondꢀdataꢀbyte
Thirdꢀdataꢀbyte
23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
1
0
1
0
0
0
0
Bꢀcounter
Aꢀcounter
PLL_CtrlI (Control Register I)
Firstꢀdataꢀbyte
Secondꢀdataꢀbyte
Thirdꢀdataꢀbyte
23 22 21 20 19 18 17 16 15 14 13 12 11 10
CPI2
9
8
7
1
6
0
5
0
4
0
3
0
2
0
1
0
0
1
0
1
0
0
W
0
0
0
0
0
CPI1
PLL_CtrlII (Control Register II)
Firstꢀdataꢀbyte
Secondꢀdataꢀbyte
Thirdꢀdataꢀbyte
23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
0
7
0
6
0
5
0
4
0
3
1
2
0
1
0
0
1
0
1
0
1
1
0
0
0
0
0
0
0
0
0
0
PLL_CtrlIII (Control Register III
)
Firstꢀdataꢀbyte
Secondꢀdataꢀbyte
Thirdꢀdataꢀbyte
23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
0
7
0
6
1
5
0
4
0
3
0
2
1
1
1
0
1
0
1
1
0
0
0
0
1
0
0
0
0
0
0
1
Reminder: Program Control Register III last.
PRELIMINARY DATA SHEET - Rev 1.0
17
02/2009
ANADIGICS [ ANADIGICS, INC ]
