AIT1042
Downconverter Main and Reference Divider Registers
TheꢀdownconverterꢀmainꢀandꢀreferenceꢀdividerꢀregistersꢀareꢀusedꢀtoꢀsetꢀtheꢀA,ꢀBꢀandꢀRꢀcountersꢀinꢀtheꢀ
downconverterꢀ synthesizer.ꢀTheꢀ outputꢀ frequencyꢀ forꢀ theꢀ synthesizerꢀ isꢀ computedꢀ usingꢀ theꢀ followingꢀ
equation:
[(64)(B) + A] fxtal
fosc
=
R
where:
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
fOSCꢀisꢀtheꢀdownconverterꢀlocalꢀoscillatorꢀ(LO2)ꢀfrequency
BꢀisꢀtheꢀdivideꢀratioꢀofꢀtheꢀBꢀcounterꢀ(2ꢀtoꢀ2047ꢀinclusive)
AꢀisꢀtheꢀdivideꢀratioꢀofꢀtheꢀAꢀcounterꢀ(0ꢀ<ꢀAꢀꢀ<ꢀP-1,ꢀAꢀ<ꢀB)
fXTALꢀisꢀtheꢀfrequencyꢀofꢀtheꢀreferenceꢀcrystalꢀoscillator
RꢀisꢀtheꢀdivideꢀratioꢀofꢀtheꢀRꢀcounterꢀ(2ꢀtoꢀ4095ꢀinclusive)
Theꢀpresetꢀmodulusꢀofꢀtheꢀprescalarꢀisꢀ64ꢀandꢀisꢀnotꢀprogrammable.
Inꢀtheꢀmainꢀdividerꢀregister,ꢀtheꢀAꢀcounterꢀisꢀsetꢀviaꢀBitsꢀ2-8ꢀandꢀtheꢀBꢀcounterꢀisꢀsetꢀwithꢀBitsꢀ9-19.ꢀInꢀtheꢀ
referenceꢀdividerꢀregister,ꢀtheꢀRꢀcounterꢀisꢀsetꢀwithꢀBitsꢀ2-13.ꢀTheꢀremainingꢀbitsꢀmustꢀuseꢀtheꢀfixedꢀvaluesꢀ
indicatedꢀinꢀTables 15 and 16.
Table 15: Downconverter Main Divider Register
LSB
MSB
PLL2_Main (Downconverter Main Divider Register)
Firstꢀdataꢀbyte
Secondꢀdataꢀbyte
Thirdꢀdataꢀbyte
23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
0
1
0
0
0
0
Bꢀcounter
Aꢀcounter
Table 16: Downconverter Reference Divider Register
PLL2_Ref (Downconverter Reference Divider Register)
Secondꢀdataꢀbyte
MSB
LSB
Firstꢀdataꢀbyte
Thirdꢀdataꢀbyte
23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
1
0
0
1
0
0
0
Rꢀcounter
0
PRELIMINARY DATA SHEET - Rev 1.0
15
02/2009
ANADIGICS [ ANADIGICS, INC ]
