AIT1042
Upconverter Main and Reference Divider Registers
TheꢀupconverterꢀmainꢀandꢀreferenceꢀdividerꢀregistersꢀareꢀusedꢀtoꢀsetꢀtheꢀA,ꢀBꢀandꢀRꢀcountersꢀinꢀtheꢀupconverterꢀ
synthesizer.ꢀꢀTheꢀoutputꢀfrequencyꢀforꢀtheꢀsynthesizerꢀisꢀcomputedꢀusingꢀtheꢀfollowingꢀequation:
where:
[(16)(B) + A] fxtal
fosc
=
R
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
fOSCꢀisꢀtheꢀupconverterꢀlocalꢀoscillatorꢀ(LO1)ꢀꢀ ꢀfrequency
BꢀisꢀtheꢀdivideꢀratioꢀofꢀtheꢀBꢀcounterꢀ(2ꢀtoꢀ2047ꢀꢀinclusive)
AꢀisꢀtheꢀdivideꢀratioꢀofꢀtheꢀAꢀcounterꢀ(0ꢀ<ꢀꢀAꢀ<ꢀP-1,ꢀꢀAꢀ<ꢀB)
fXTALꢀisꢀtheꢀfrequencyꢀofꢀtheꢀreferenceꢀcrystalꢀoscillator
RꢀisꢀtheꢀdivideꢀratioꢀofꢀtheꢀRꢀcounterꢀ(2ꢀtoꢀ1023ꢀinclusive)
Theꢀpresetꢀmodulusꢀofꢀtheꢀprescalarꢀisꢀ16ꢀandꢀisꢀnotꢀprogrammable.
Inꢀtheꢀmainꢀdividerꢀregister,ꢀtheꢀAꢀcounterꢀisꢀsetꢀviaꢀBitsꢀ2-8ꢀandꢀtheꢀBꢀcounterꢀisꢀsetꢀwithꢀBitsꢀ9-19.ꢀInꢀtheꢀ
referenceꢀdividerꢀregister,ꢀtheꢀRꢀcounterꢀisꢀsetꢀwithꢀBitsꢀ2-11.ꢀTheꢀremainingꢀbitsꢀmustꢀuseꢀtheꢀfixedꢀvaluesꢀ
indicatedꢀinꢀTablesꢀ13ꢀandꢀ14.
Table 13: Upconverter Main Divider Register
PLL1_Main (Upconverter Main Divider Register)
LSB
MSB
Firstꢀdataꢀbyte
Secondꢀdataꢀbyte
Thirdꢀdataꢀbyte
23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
1
0
1
0
0
0
0
Bꢀcounter
Aꢀcounter
LSB
MSB
Table 14: Upconverter Reference Divider Register
PLL1_Ref (Upconverter Reference Divider Register)
Firstꢀdataꢀbyte
Secondꢀdataꢀbyte
Thirdꢀdataꢀbyte
23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
1
0
0
0
0
0
1
0
0
1
0
0
0
0
0
Rꢀcounter
PRELIMINARY DATA SHEET - Rev 1.0
14
02/2009
ANADIGICS [ ANADIGICS, INC ]
