-25 / I-25
Symbol
Parameter
Input5 to non-registered output
Units
Min
Max
25
25
tPD
tOE
tOD
ns
ns
ns
Input5 to output enable6
Input5 to output disable6
25
tCO1
tCO2
tCF
tSC
tHC
tCL, tCH
tCP
fMAX1
fMAX2
fMAX3
tAW
Clock to Output
15
35
9
ns
ns
ns
ns
ns
ns
ns
MHz
MHz
MHz
ns
ns
ns
Clock to comb. output delay via internal registered feedback
Clock to Feedback
Input5 or feedback setup to clock
Input5 hold after clock
15
0
13
Clock low time, clock high time8
Min clock period Ext (tSC + tCO1
Internal feedback (1/tSC + tCF)11
External feedback (1/tCP)11
No feedback (1/tCL + tCH)11
)
30
41.6
33.3
38.4
25
Asynchronous Reset Pulse Width
tAP
tAR
tRESET
Input5 to Asynchronous Reset
25
25
5
Asynchronous Reset recovery time
Power-on reset time for registers in clear state12
µs
Switching Waveforms
Inputs, I/O,
Registered Feedback,
Synchronous Preset
Clock
Asynchronous
Reset
Registered
Outputs
Combinatorial
Outputs
Notes:
1. Minimum DC input is -0.5V, however, inputs may undershoot to -2.0V for peri-
ods less than 20 ns.
8. Test conditions assume: signal transition times of 3ns or less from the 10% and
90% points, timing reference levels of 1.5V (Unless otherwise specified).
9. Test one output at a time for a duration of less than 1 second.
10. ICC for a typical application: This parameter is tested with the device pro-
grammed as an 8-bit Counter.
2. VI and VO are not specified for program/verify operation.
3. Test Points for Clock and VCC in t
R and tF are referenced at the 10% and 90%
levels.
4. I/O pins are 0V and VCC
.
11. Parameters are not 100% tested. Specifications are based on initial character-
ization and are tested after any design process modification that might affect oper-
ational frequency.
5. “Input” refers to an input pin signal.
6. tOE is measured from input transition to VREF±0.1V,
TOD is measured from input transition to VOH-0.1V or VOL+0.1V; VREF=VL.
12. All input at GND.
7. Capacitances are tested on a sample basis.
Anachip Corp.
www.anachip.com.tw
Rev. 1.0 Dec 16, 2004
8/10
ANACHIP [ ANACHIP CORP ]
