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AS1544 参数 Datasheet PDF下载

AS1544图片预览
型号: AS1544
PDF下载: 下载PDF文件 查看货源
内容描述: 8/4通道, 1 MSPS , 12位ADC,序 [8/4-Channel, 1 Msps, 12-Bit ADC with Sequencer]
分类和应用:
文件页数/大小: 29 页 / 1031 K
品牌: AMSCO [ AMS(艾迈斯) ]
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AS1543/44  
Data Sheet - Detailed Description  
Auto Shutdown (PM1 = 0, PM0 = X)  
In this mode, the AS1543/44 automatically enters shutdown after the 14th SLK falling edge of each conversion is  
updated. When the device is in shutdown mode, the track/hold circuitry is in hold mode.  
Note: The control register maintains its data while in shutdown mode.  
Figure 34 shows the operation of the AS1543/44 when it is in automatic shutdown mode The AS1543/44 remains in  
shutdown until the next CSN falling edge it receives. On this CSN falling edge, the track and hold that was in hold while  
the device was in shutdown will return to track.  
Note: Wake-up time from auto shutdown is 1µs.  
Figure 34. Auto Shutdown Mode Operation  
Device begins to power  
up on falling CSN edge  
and remains powered-up  
on PM1=1 and PM0=1  
Device enters shutdown  
on the 14th SCLK falling  
edge as PM1 = 0  
Device is fully  
powered up  
Device enters automatic  
shutdown on 14th SCLK  
falling edge as PM1 = 0  
Dummy Conversion  
1
Valid Conversion  
14 16  
CSN  
1
14 16  
14 16  
1
SCLK  
DOUT  
Channel ID Bits + Conversion Results  
Data into Control/Shadow Register  
Invalid Data  
Channel ID Bits + Conversion Results  
Data into Control/Shadow Register  
Data into Control/Shadow Register  
DIN  
Notes:  
1. Control register data is loaded on the 1st 13 SCLK cycles.  
2. Set control register bits PM1 = 1 and PM0 = 1 to keep the device in normal mode.  
When running the AS1543/44 with a 20MHz clock, one dummy cycle of 1µs (see Figure 34) (16 SCLKs plus  
Track&Hold aquisation time) should be sufficient to ensure the part is fully powered up.  
This dummy cycle effectively halves the throughput rate, with every other conversion result being valid. In this mode,  
the power consumption of the part is greatly reduced with the part entering shutdown at the end of each conversion.  
Note: The end of shutdown can be controlled by the CSN signal.  
Power vs. Throughput Rate  
By operating the AS1543/44 in auto shutdown (see page 23) the average power consumption of the ADC decreases at  
lower throughput rates. The Power vs. Throughput Rate graph in the Typical Operating Characteristics section shows  
how as the throughput rate is reduced, the part remains in its shutdown state longer and the average power consump-  
tion over time drops accordingly.  
If the AS1543/44 is operated in a continuous sampling mode with a throughput rate of 100ksps and a SCLK of 20 MHz  
(VDD = 5V), with bit PM1 (page 14) = 0, i.e., the device is in auto shutdown mode (see page 23), then the power con-  
sumption is calculated as follows:  
The maximum power dissipation during normal operation is 18.4mW (VDD = 5.25V). If the power-up time from auto  
shutdown is one dummy cycle (i.e., 1µs) and the remaining conversion time is another cycle (i.e., 1µs) then the  
AS1543/44 will dissipate approximately 18.4mW for 2µs during each conversion cycle. For the remainder of the con-  
version cycle (8µs), the device remains in shutdown mode. The AS1543/44 will dissipate approximately 2.5µW for the  
remaining 8µs of the conversion cycle. If the throughput rate is 100ksps, the cycle time is 10µs and the average power  
dissipated during each cycle is:  
((2/10) x 18.4mW) + ((8/10) x 2.5µW) = 3.682mW  
(EQ 1)  
www.austriamicrosystems.com  
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