AS1543/44
Data Sheet - Detailed Description
However, if bit WEAK/TRIN is set to 1, then although DOUT is driven with address bit ADDR3 since the last conver-
sion, it is nevertheless so weakly driven that another device may still take control of the bus. It will not lead to a bus
contention (e.g., a 10 kΩ pull-up or pull-down resistor would be sufficient to overdrive the logic level of ADDR3
between conversions) and all 16 channels may be identified. However, if this does happen and another device takes
control of the bus, it is not guaranteed that DOUT will be fully driven to ADDR3 again in time for the read operation
when control of the bus is taken back.
This is useful if using an automatic sequence mode to identify channel-result pairs. Obviously, if only the first eight
channels are in use, then address bit ADDR3 does not need to be decoded, and whether it is successfully clocked in
as a 1 or 0 will not matter as long as it is still counted by the DSP as the MSB of the 16-bit serial transfer.
Power Modes
The AS1543/44 can be operated in 2 different modes:
- Normal Mode (see page 22)
- Auto Shutdown (see page 23)
These modes are designed to provide flexible power management options, and can be selected to optimize the power
dissipation and throughput-rate ratio for differing application requirements. The mode of operation of the AS1543/44 is
controlled by bits PM1, PM0 (page 14) of the control register.
Note: When power supplies are first applied to the AS1543/44, internal power-on reset circuitry sets the device for
Auto Shutdown (PM1 = 0, PM0 = x). The AS1543/44 remains in shutdown the first CSN falling edge is
received.
Normal Mode (PM1 = 1, PM0 = 1)
This mode is intended for the fastest throughput rate performance as the user does not have to worry about any
power-up times with the AS1543/44 remaining fully powered at all times. Figure 33 shows the operation of the
AS1543/44 in normal mode.Conversion is initiated on the falling edge of CSN and the track and hold will enter hold
mode.
The data presented to pin DIN during the first 13 clock cycles of the data transfer is loaded to the control register (if bit
WRITE (page 14) is set to 1). If bit SEQ (page 14) = 0, and bit SHADOW (page 14) = 1 on the previous write, data pre-
sented on pin DIN during the first 16 SCLK cycles is loaded into the shadow register. The device will remain fully
powered up in normal mode at the end of the conversion as long as bits PM1, PM0 (page 14) are set to 1 in the write
transfer during that conversion.
To ensure continued operation in normal mode, bits PM1 and PM0 are loaded with 1 on every data transfer. Sixteen
serial clock cycles are required to complete the conversion and access the conversion result. The track and hold will
go back into track on the 14th SCLK falling edge.
Once a data transfer is complete (DOUT has returned to tri-state, bit WEAK/TRIN (page 14) = 0), another conversion
can be initiated after the quiet time (tQUIET) has elapsed by bringing CSN low again.
Figure 33. Normal Mode Operation
CSN
SCLK
DOUT
DIN
Channel ID Bits + Conversion Results
Data into Control/Shadow Register
Notes:
1. Control register data is loaded on the 1st 13 SCLK cycles.
2. Shadow register data is loaded on the 1st 16 SCLK cycles.
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