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AS1544 参数 Datasheet PDF下载

AS1544图片预览
型号: AS1544
PDF下载: 下载PDF文件 查看货源
内容描述: 8/4通道, 1 MSPS , 12位ADC,序 [8/4-Channel, 1 Msps, 12-Bit ADC with Sequencer]
分类和应用:
文件页数/大小: 29 页 / 1031 K
品牌: AMSCO [ AMS(艾迈斯) ]
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AS1543/44  
Data Sheet - Detailed Description  
Shadow Register  
The shadow register is a 16-bit, write-only register. Data is loaded from pin DIN of the AS1543/44 on the falling edge of  
SCLK. The data is transferred on pin DIN at the same time as a conversion result is read from the device. This requires  
16 serial falling edges for the data transfer.  
The information is clocked into the shadow register (provided bits SEQ (page 14) and SHADOW (page 14) were set to  
0, 1 respectively), in the previous write to the control register.  
Each bit represents one of the input channels (VIN0 through VIN3/VIN7). Multiple channels can be selected for continu-  
ous cycling on each consecutive CSN falling edge after a write to the shadow register. To select a sequence of chan-  
nels, the associated bit must be set for each analog input channel.  
The AS1543/44 will continuously cycle through the selected channels in ascending order, beginning with the lowest  
channel, until a write operation occurs (i.e., bit WRITE (page 14) is set to 1) with bits SEQ and SHADOW configured in  
any way except 1, 0 (see Table 11 on page 17).  
Table 12. 16-Bit Shadow Register Format, AS1543  
0
15  
(MSB)  
14  
13  
12  
11  
10  
9
8
7
6
5
4
3
2
1
(LSB)  
VIN0  
VIN1  
VIN2  
VIN3  
VIN4  
VIN5  
VIN6  
VIN7  
VIN0  
VIN1  
VIN2  
VIN3  
VIN4  
VIN5  
VIN6  
VIN7  
Table 13. 16-Bit Shadow Register Format, AS1544  
0
15  
(MSB)  
14  
13  
12  
11  
10  
9
8
7
6
5
4
3
2
1
(LSB)  
VIN0  
VIN1  
VIN2  
VIN3  
VIN0  
VIN1  
VIN2  
VIN3  
VIN0  
VIN1  
VIN2  
VIN3  
VIN0  
VIN1  
VIN2  
VIN3  
Direct Conversion (SEQ = 0, SHADOW = 0)  
Figure 28 shows the normal flow of an ADC with multiple input channels selected, where each serial transfer selects  
the next channel for conversion. In this mode of operation, the sequencer function is not used.  
Figure 28. Bit SEQ = 0, Bit SHADOW = 0 Flowchart  
Power On  
DOUT: Dummy Conversion Result  
DIN: Write to Control Register;  
CSN Falling  
Bit WRITE = 1;  
Edge  
Select Coding, Range, SE/FDN, WEAK/TRIN and Power Mode;  
Select Channel ADDR3:ADDR0 (see Table 5 on page 14) for  
Conversion  
Bit SEQ = 0, Bit SHADOW = 0  
Bit WRITE = 1, Bit SEQ = 0, Bit SHADOW = 0  
Bit WRITE = 0  
Bit WRITE = 0  
Bit WRITE = 1  
Bit SEQ = 0  
Bit SHADOW = 0  
DOUT: Conversion Result from  
previously selected ADDR3:ADDR0  
Channel  
DOUT: Conversion Result from  
previously selected ADDR3:ADDR0  
Channel  
Bit WRITE = 1,  
Bit SEQ = 0,  
Bit SHADOW = 0  
CSN Falling  
Edge  
Bit WRITE = 0  
DIN: Write to Control Register;  
Bit WRITE = 1;  
Select Coding, Range, SE/FDN, WEAK/  
TRIN and Power Mode;  
Select Channel ADDR3:ADDR0 for  
Conversion  
Bit SEQ = 0, Bit SHADOW = 0  
CSN Falling  
Edge  
Exit this flow whenever WRITE = 1 and NOT (SEQ = 0, SHADOW = 0)  
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