AS1536/AS1537
Datasheet - Application Information
Unlike the SPI interface, which requires two 1-byte reads to acquire the 12 data bits from the AS1536/AS1537, QSPI
allows the minimum number of clock cycles necessary to clock in the data. The devices require 13 clock cycles from
the microprocessor to clock out the 12 data bits with no trailing zeros (see Figure 36).
Note: The maximum clock frequency to ensure compatibility with QSPI is 2.097MHz.
Figure 36. QSPI Serial Interface Timing (CPOL = CPHA = 0)
SCLK
CSN
tCONV
EOC
High-Z
when CSN
is High
DOUT
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
MSB
LSB
Layout Considerations
The AS1536/AS1537 require proper layout and design procedures for optimum performance.
ꢀ
ꢀ
Use printed circuit boards; wirewrap boards should not be used.
Separate analog and digital traces from each other. Analog and digital traces should not run parallel to each other
(especially clock traces).
ꢀ
ꢀ
Digital traces should not run beneath the AS1536/AS1537.
Use a single-point analog ground at GND, separate from the digital ground (see Figure 37). Connect all other ana-
log grounds and DGND to this star ground point for further noise reduction. No other digital system ground should
be connected to this single-point analog ground. The ground return to the power supply for this ground should be
low impedance and as short as possible for noise-free operation.
ꢀ
High-frequency noise in the VDD power supply may affect the AS1536/AS1537 high-speed comparator. Bypass
this supply to the single-point analog ground with 0.1µF and 4.7µF bypass capacitors (see Figure 37). The bypass
capacitors should be placed as close to the device as possible for optimum power supply noise-rejection. If the
power supply is very noisy, a 10Ω resistor can be connected as a low-pass filter to attenuate supply noise.
Figure 37. Recommended Ground Design
+3V
+3V
Digital
Circuitry
GND
DGND
Power
Supplies
5
GND
GND
AS1536/
AS1537
4.7µF
0.1µF
10Ω
(Optional)
+
1
+3V
VDD
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