AS1536/AS1537
Datasheet - Detailed Description
9. Extra clock pulses occurring after the conversion result has been clocked out, and prior to a rising edge of CSN,
produce trailing zeros at DOUT and have no effect on the conversion process.
10. For minimum cycle time, clock out the data with 12.5 clock cycles at full speed using the rising edge of DOUT as
the EOC signal. Pull CSN high after reading the conversion’s LSB. After the specified minimum time (tCS) CSN can
be pulled low to initiate the next conversion.
Figure 25. Serial Interface Standard Cycle Timing Diagram
CSN
SCLK
B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
DOUT
Conversion
In Progress
Trailing
0s
Interface
EOC
Clock Out Serial Data
Track
Idle
Idle
Track/Hold
Stage
Track
Hold
Hold
tCONV
7.5µs
0µs
12.5 x 0.476µs = 5.95µs
Total = 13.7µs
0µs
tCS
0.24µs
Cycle Time
Figure 26. Serial Interface Minimum Cycle Timing Diagram
CSN
SCLK
B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
Clock Out Serial Data
B11 B10
DOUT
Conversion
In Progress
Interface
EOC
0µs
Idle
Idle
Track/Hold
Stage
Track
Hold
Hold
Track
tCONV
7.5µs
12.5 x 0.476µs = 5.95µs
Total = 13.7µs
tCS
0.24µs
Cycle Time
Figure 27. Detailed Serial Interface Timing Diagram
tCS
CSN
tCSO
tCH
SCLK
tDO
tTR
tCL
tCONV
tDV
DOUT
B2
B1
B0
tSTR
Track/Acquire
Hold
Track/Acquire
Internal
Track/Hold
tAP
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