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AS1530_1 参数 Datasheet PDF下载

AS1530_1图片预览
型号: AS1530_1
PDF下载: 下载PDF文件 查看货源
内容描述: 12位,单电源,低功耗, 400 /高达300ksps , 8通道A / D转换器 [12-Bit, Single-Supply, Low-Power, 400/300ksps, 8-Channel A/D Converters]
分类和应用: 转换器
文件页数/大小: 29 页 / 1091 K
品牌: AMSCO [ AMS(艾迈斯) ]
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AS1530/AS1531  
Data Sheet - Electrical Characteristics  
Table 3. AS1530 Electrical Characteristics (Continued)  
Symbol  
Parameter  
Conditions  
Min  
Typ  
Max Units  
Capacitive Bypass at  
REFADJ  
CBYPREF  
ADJ  
0.01  
10  
µF  
REFADJ Output Voltage  
REFADJ Input Range  
1.22  
V
For small adjustments, from 1.22V  
To power down the internal reference  
±100  
mV  
REFADJ Buffer Disable  
Threshold  
VDD1 -  
1
1.4  
1.0  
V
Buffer Voltage Gain  
2.045  
200  
V/V  
External Reference: Reference buffer disabled, reference applied to pin REF  
VDD1  
+
50mV  
REF Input Voltage Range 8  
V
VREF = 2.50V,  
fSCLK = 6.4MHz  
350  
REF Input Current  
µA  
VREF = 2.50V, fSCLK = 0  
320  
5
Power-Down, fSCLK = 0  
Digital Inputs: DIN, SCLK, CSN  
0.7 x  
VDD  
VINH  
VINL  
Input High Voltage  
Input Low Voltage  
V
V
0.3 x  
VDD  
VHYST  
IIN  
Input Hysteresis  
Input Leakage  
0.2  
5
V
VIN = 0 or VDD2  
-1  
+1  
µA  
pF  
CIN  
Input Capacitance  
Digital Outputs: DOUT, SSTRB  
VOL  
VOH  
IL  
Output Voltage Low  
Output Voltage High  
ISINK = 5mA  
ISOURCE = 1mA  
CSN = VDD2  
CSN = VDD2  
0.45  
+10  
V
V
4
Tri-State Leakage Current  
Tri-State Output Capacitance  
-10  
µA  
pF  
COUT  
5
Power Supply  
VDD1,  
VDD2,  
Positive Supply Voltage 9  
4.5  
5.5  
3.3  
V
VDD3  
Normal Operation with  
2.8  
External Reference 10  
Normal Operation with  
Internal Reference 10  
mA  
IVDD1,  
IVDD2,  
IVDD3  
3.3  
0.4  
3.8  
0.8  
VDD1 = VDD2 =  
VDD3 = 5.5V  
Supply Current  
Reduced-Power Mode 11  
Full Power-Down Mode  
0.5  
2
µA  
PSR  
Power-Supply Rejection  
VDD1 = VDD2 = VDD3 = 5V ±10%  
-2  
±0.1  
+2  
mV  
1. Tested at VDD1 = VDD2 = VDD3 = +5V, COM = GND, bit RANGE (page 15) = 1, single-ended input mode.  
2. Relative accuracy is the deviation of the analog value at any code from its theoretical value after the gain error  
and offset error have been nulled.  
3. Offset nulled.  
4. Ground on channel; sinewave applied to all off channels.  
5. Conversion time is defined as the number of clock cycles multiplied by the clock period; clock has 50% duty  
cycle.  
6. The absolute voltage range for the analog inputs (CH0:CH7, and COM) is from GND to VDD1.  
7. External load should not change during conversion for specified accuracy. Guaranteed specification of 4mV/mA  
is a result of production test limitations.  
8. AS1530/AS1531 performance is limited by the device noise floor, typically 300µVp-p.  
www.austriamicrosystems.com  
Revision 1.02  
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