AS1530/AS1531
Data Sheet - Electrical Characteristics
2. Relative accuracy is the deviation of the analog value at any code from its theoretical value after the gain error
and offset error have been nulled.
3. Offset nulled.
4. Ground on channel; sinewave applied to all off channels.
5. Conversion time is defined as the number of clock cycles multiplied by the clock period; clock has 50% duty
cycle.
6. The absolute voltage range for the analog inputs (CH0:CH7, and COM) is from GND to VDD1.
7. External load should not change during conversion for specified accuracy. Guaranteed specification of 2mV/mA
is a result of production test limitations.
8. AS1530/AS1531 performance is limited by the device noise floor, typically 300µVp-p.
9. Electrical characteristics are guaranteed from VDD1(MIN) = VDD2(MIN) = VDD3(MIN) to VDD1(MAX) = VDD2(MAX) =
VDD3(MAX). For operations beyond this range, see Typical Operating Characteristics on page 11. For guaranteed
specifications beyond the limits, contact austriamicrosystems, AG.
10. AIN = mid-scale; bit RANGE (page 15) = 1; tested with 20pF on DOUT, 20pF on SSTRB, and fSCLK = 4.8MHz
@ GND to VDD2.
11. SCLK = DIN = GND, CSN = VDD2.
Timing Characteristics
Table 5. AS1530 Timing Characteristics – (Figures 3, 4, 21, 23; VDD1 = VDD2 = VDD3 = +4.5 to +5.5V; TAMB = TMIN to
TMAX (unless otherwise specified).
Symbol
tCP
Parameter
Conditions
Min
156
62
62
35
0
Typ
Max
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SCLK Period
tCH
SCLK Pulse Width High
SCLK Pulse Width Low
DIN to SCLK Setup
tCL
tDS
tDH
DIN to SCLK Hold
tCSS
tCS0
tDOH
tSTH
tSTV
tDOV
tDOD
tSTD
tDOE
tSTE
tCSW
CSN Fall to SCLK Rise Setup
SCLK Rise to CSN Fall Ignore
SCLK Rise to DOUT Hold
SCLK Rise to SSTRB Hold
SCLK Rise to DOUT Valid
SCLK Rise to SSTRB Valid
CSN Rise to DOUT Disable
CSN Rise to SSTRB Disable
CSN Fall to DOUT Enable
CSN Fall to SSTRB Enable
CSN Pulse Width High
35
35
10
10
CLOAD = 20pF
CLOAD = 20pF
CLOAD = 20pF
CLOAD = 20pF
CLOAD = 20pF
CLOAD = 20pF
CLOAD = 20pF
CLOAD = 20pF
20
20
80
80
65
65
65
65
10
10
100
Table 6. AS1531 Timing Characteristics – (Figures 3, 4, 21, 23; VDD1 = VDD2 = VDD3 = +2.7 to +3.6V; TAMB = TMIN to
TMAX (unless otherwise specified).
Symbol
tCP
Parameter
Conditions
Min
208
83
83
45
0
Typ
Max
Units
ns
SCLK Period
tCH
SCLK Pulse Width High
SCLK Pulse Width Low
DIN to SCLK Setup
ns
tCL
ns
tDS
ns
tDH
DIN to SCLK Hold
ns
tCSS
tCS0
tDOH
tSTH
CSN Fall to SCLK Rise Setup
SCLK Rise to CSN Fall ignore
SCLK Rise to DOUT Hold
SCLK Rise to SSTRB Hold
45
45
13
13
ns
ns
CLOAD = 20pF
CLOAD = 20pF
20
20
ns
ns
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