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AS1358_04 参数 Datasheet PDF下载

AS1358_04图片预览
型号: AS1358_04
PDF下载: 下载PDF文件 查看货源
内容描述: 150毫安/ 300毫安,超低噪声,高PSRR低压降稳压器 [150mA/300mA, Ultra-Low-Noise, High-PSRR Low Dropout Regulators]
分类和应用: 稳压器
文件页数/大小: 17 页 / 1308 K
品牌: AMSCO [ AMS(艾迈斯) ]
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AS1358 / AS1359  
Datasheet - Application Information  
9.6.2 Output Capacitor ESR  
The series regulator is a negative feedback amplifier, and as such is conditionally stable. The ESR of the output capacitor is usually used to  
cancel one of the open loop poles of the error amplifier in order to produce a single pole response. Excessive ESR values may actually cause  
instability by excessive changes to the closed loop unity gain frequency crossover point. The range of ESR values for stability is usually shown  
either by a plot of stable ESR versus load current, or a limit statement in the datasheet.  
Some ceramic capacitors exhibit large capacitance and ESR variations with temperature. Z5U and Y5V capacitors may be required to ensure  
stability at temperatures below TAMB = -10ºC. With X7R or X5R capacitors, a 1.0µF capacitor should be sufficient at all operating temperatures.  
Larger output capacitor values (2.2µF max) help to reduce noise and improve load transient-response, stability and power-supply rejection.  
9.6.3 Input Capacitor  
An input capacitor at VIN is required for stability. It is recommended that a 1.0µF capacitor be connected between the AS1358 / AS1359 powr  
supply input pin VIN and ground (capacitance value may be increased without limit subject to ESR limits). This capacitor must be located t a  
distance of not more than 1cm from the VIN pin and returned to a clean analog ground. Any good quality ceramic, tantalum, or film capator m
be used at the input.  
9.6.4 Noise  
The regulator output is a DC voltage with noise superimposed on the output. The noise comes from three sources; the refrencethe error  
amplifier input stage, and the output voltage setting resistors. Noise is a random fluctuation and if not minimized in somapplcations, will  
produce system problems. The AS1358/9 architecture provides enhance noise eduction when an external 10nF caacitor iconnected between  
Bypass and Output pins, and 1µF connected as the output capacitor.  
The leakage current going into the BYPASS pin should be less than 10nA. Increaing the capacitance slightly deceases the output noise.  
Values above 0.1µF and below 0.001µF are not recommended.  
9.6.5 Transient Response  
The series regulator is a negative feedback system, and therefore any change at the output wtake a finite time to be corrected by the error  
loop. This “propagation time” is related to the bandwidth of the errooop. The initial rese to an output transient comes from the output  
capacitance, and during this time, ESR is the dominant mehanism causing voltge traienat the output. More generally:  
VTRANSIENT = IOUPUT RESR Units are Volts, Amps, Ohms.  
(EQ 14)  
Thus an initial +50mA change of output currnt ill produce a -12mV transint when the ESR=240m. Remember to keep the ESR within  
stability recommendations when reducing ESR adding multiple paoutpt capacitors.  
After the initial ESR transient, there follows a voltage droop during tthat the LDO feedback loop takes to respond to the output change.  
This drift is approximately linear in time and sums with the ESR contribution to make a total transient variation at the output of:  
T
---------------  
VTRANSIENT = IOUTPUT RESR  
+
Units are Volts, Seconds, Farads, Ohms.  
(EQ 15)  
CLOAD  
Where:  
CLOAD is output capacitor  
T = Propagation delay of the LDO  
This shows why it is convenient to incase the output capacitor value for a better support for fast load changes. Of course the formula holds for  
t < “propagation time”, so that a faer LDO needs a smaller cap at the load to achieve a similar transient response. For instance 50mA load  
current step produces 50mV oput drp if the LDO response is 1usec and the load cap is 1µF.  
There is also a steay sate rror caused by the finite output impedance of the regulator. This is derived from the load regulation specification  
discussed above.  
9.6.6 Turn OTime  
This specon defines the time taken for the LDO to awake from shutdown. The time is measured from the release of the enable pin to the  
tie that toutut voltage is within 5% of the final value. It assumes that the voltage at VIN is stable and within the regulator Min and Max limits.  
Shudown reduces the quiescent current to very low, mostly leakage values (<1µA).  
9.6.7 Thermal Protection  
To prevent operation under extreme fault conditions, such as a permanent short circuit at the output, thermal protection is built into the device.  
Die temperature is measured, and when a 160ºC threshold is reached, the device enters shutdown. When the die cools sufficiently, the device  
will restart (assuming input voltage exists and the device is enabled). Hysteresis of 15ºC prevents low frequency oscillation between start-up and  
shutdown around the temperature threshold.  
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Revision 1.5  
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