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AS1310_12 参数 Datasheet PDF下载

AS1310_12图片预览
型号: AS1310_12
PDF下载: 下载PDF文件 查看货源
内容描述: 超低静态电流,滞回DC-DC升压转换器 [Ultra Low Quiescent Current, Hysteretic DC-DC Step-Up Converter]
分类和应用: 转换器升压转换器
文件页数/大小: 20 页 / 1598 K
品牌: AMSCO [ AMS(艾迈斯) ]
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AS1310  
Datasheet - Detailed Description  
8.1.4 Input Capacitor Selection  
The input capacitor supports the triangular current during the on-time of the power switch, and maintains a broadly constant input voltage during  
this time. The capacitance value is obtained from choosing a ripple voltage during the on-time of the power switch. Additionally, ripple voltage is  
generated by the equivalent series resistance (ESR) of the capacitor. For worst case, use maximum peak current values from the datasheet.  
IPEAKTON  
-------------------------  
CIN  
=
(EQ 15)  
VRIPPLE  
Using TON = 1µs, and IPEAK = 480mA, and VRIPPLE = 50mV, EQ 15 yields:  
CIN = 9.6µF  
Nearest preferred would be 10µF.  
VPK _ RIPPLE _ ESR = IPK RESR  
(EQ
Typically, the ripple due to ESR is not dominant. ESR for the recommended capacitors (Murata GMR), ESR = 5mΩ to 10mΩ. For he A1310,  
maximum peak current is 480mA. Ripple due to ESR is 2.4mV to 4.8mV.  
Ripple at the input propagates through the common supply connections, and if too high in value can cause problems elewherin the system.  
The input capacitance is an important component to get right.  
8.1.5 Output Capacitor Selection  
The output capacitor supports the triangular current during the off-time of the pwer swit(inductor discharge period), and also the load current  
during the wait time (Region D in Figure 13) and on-time (Region A in Figure 13) othe power switch.  
ILOAD (TO+TWAIT  
(10.99)VOUT _ NOM  
)
COUT  
=
(EQ 17)  
Note: There is also a ripple component due to the equivalent series resistance (ESf the capacitor.  
8.2 Summary  
User Application Defines: VINmin, VINmaOUTmin, VOUTmax, ILOADmin, ILOADmax  
Inductor Selection:  
Select Max on-time = 0.5µs to 3µs for AS1310. Use (EQ 3) tcalculate inductor value.  
Use (EQ 5) to determine off-time.  
Use (EQ 6) to check that power delivery matches load rquirements assume 70% conversion efficiency.  
Use (EQ 13) to find overall timing period value f T in VIN and max VOUT for maximum load conditions.  
Input Capacitor Selection: Choose ripple value and use (EQ 14) to find the value.  
Output Capacitor Selection: Deterine TWAIT via (EQ 6) or (EQ 13), and use (EQ 16) to find the value.  
www.austriamicrosystems.com/DC-DC_Step-Up/AS1310  
Revision 1.8  
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