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AS1160 参数 Datasheet PDF下载

AS1160图片预览
型号: AS1160
PDF下载: 下载PDF文件 查看货源
内容描述: 为20MHz - 66MHz的10位总线, IEEE 1149.1 ( JTAG )标准的LVDS串行器/解串器 [20MHz - 66MHz, 10-Bit Bus, IEEE 1149.1 (JTAG) Compliant LVDS Serializer/Deserializer]
分类和应用:
文件页数/大小: 29 页 / 902 K
品牌: AMSCO [ AUSTRIAMICROSYSTEMS AG ]
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AS1160/AS1161
Datasheet - P i n o u t
Figure 3. AS1161 Pin Assignments (Top View)
A1
DGND
B1
A2
A3
A4
A5
A6
A7
N/C REFCLK AGND ROUT1 DGND DVDD
B2
B3
B4
B5
B6
B7
AVDD AGND RCKR/FN ROUT2 DGND ROUT3 DVDD
C1
RI-
D1
REN
E1
C2
AVDD
D2
RI+
E2
C3
N/C
D3
PWDNN
E3
N/C
F3
C4
C5
C6
C7
ROUT0 DVDD DVDD ROUT4
D4
N/C
E4
DGND
F4
D5
D6
D7
DVDD ROUT5 DGND
E5
TCK
F5
E6
E7
LOCKN RCLK
F1
AVDD
G1
AVDD
F2
AVDD
G2
TRSTN DGND
F6
TDI
G6
F7
ROUT6
G7
TMS
AGND AGND ROUT8
G3
G4
G5
AGND DGND ROUT9 ROUT7 TDO
Table 2. AS1161 Pin Descriptions
Pin Name
Description
ROUT0:ROUT9
Data Output.
±4mA CMOS level outputs.
Recovered Clock Rising/Falling Strobe Select.
LVTTL level input. Selects RCLK
active edge for strobing of R
OUT0
:R
OUT9
data.
RCKR/FN
1 = Rising edge.
0 = Falling edge.
Reference Clock Input.
LVTTL level input. Input for 20MHz - 66MHz system clock.
REFCLK
+ Serial Data Input.
Non-inverting Bus LVDS differential input.
RI+
- Serial Data Input.
Inverting Bus LVDS differential input.
RI-
Powerdown.
LVTTL level input. Driving this pin low shuts down the PLL, tri-states
PWDNN
the outputs and puts the device into low power sleep mode.
Lock.
CMOS level output. This signal goes low when the deserializer PLL locks onto
LOCKN
the embedded clock edge.
Recovered Clock.
CMOS level output. Parallel data rate clock recovered from
RCLK
embedded clock. Used to strobe R
OUT0
:R
OUT9
.
Output Enable.
LVTTL level input. If REN is set to logic low R
OUT0
:R
OUT9
and RCLK
See
REN
are in tri-state condition.
+3.0V to +3.6V Digital Circuit Power Supply.
This is the supply for all digital
DVDD
circuitry.
Digital Circuit Ground
DGND
+3.0V to +3.6V Analog Power Supply
(PLL and Analog Circuits). AVDD and DVDD
should be at the same potential and must not be more than 0.3V apart even on
AVDD
transient basis. Both supplys should be decoupled by a capacitor of typically 10nF.
Analog Ground
(PLL and Analog Circuits).
AGND
IEEE 1149.1 Test Data Input
TDI
IEEE 1149.1 Test Data Output
TDO
IEEE 1149.1 Test Mode Select Input
TMS
IEEE 1149.1 Test Clock Input
TCK
IEEE 1149.1 Test Reset Input
TRSTN
No Connection.
Leave open-circuit, do not connect these pins.
N/C
Pin Number
Revision 1.01
4 - 29