AS1160/AS1161
Datasheet - P i n o u t
4 Pinout
Pin Assignments and Descriptions
Figure 2. AS1160 Pin Assignments (Top View)
A1
DGND
B1
DIN1
C1
DIN3
D1
DIN5
E1
DIN7
F1
TDI
G1
TDO
A2
N/C
B2
N/C
C2
A3
A4
A5
A6
AVDD
B6
A7
N/C
B7
AVDD
C7
DIN0 SYNC1 AVDD
B3
B4
B5
SYNC2 AVDD
C3
C4
AGND AGND
C5
N/C
D5
DO-
E5
C6
DGND DVDD DVDD
D2
DIN2
E2
DIN6
F2
DIN8
G2
D3
DIN4
E3
TMS
F3
TCK
G3
D4
N/C
E4
TCLK
F4
DIN9
G4
AGND PWDNN
D6
DEN
E6
D7
DO+
E7
DVDD DGND AGND
F5
DGND
G5
F6
N/C
G6
N/C
F7
AGND
G7
N/C
TRSTNTCKR/FN DGND AVDD
Table 1. AS1160 Pin Descriptions
Pin Number
Description
Data Input.
LVTTL levels inputs. Data on these pins are loaded into a 10-bit input
DIN0:DIN9
register.
Transmit Clock Rising/Falling Strobe Select.
LVTTL level input. Selects TCLK
active edge for strobing of D
INx
data.
TCKR/FN
1 = Rising edge.
0 = Falling edge.
+ Serial Data Output.
Non-inverting Bus LVDS differential output.
DO+
- Serial Data Output.
Inverting Bus LVDS differential output.
DO-
Serial Data Output Enable.
LVTTL level input. If DEN is set to logic low the Bus LVDS
DEN
outputs are in tri-state condition.
Powerdown.
LVTTL level input. Driving this pin low shuts down the PLL, tri-states the
PWDNN
outputs and puts the device into low power sleep mode.
Transmit Clock.
LVTTL level input. Input for 20MHz to 66MHz system clock.
TCLK
Synchronization.
LVTTL level input. Assertion of SYNC (high) for at least 5 clock
cycles to be transmit a synchronization signal (SYNCPAT) on the Bus LVDS serial
SYNC1,
SYNC2
output. Synchronization symbols continue to be sent if SYNCx continues to be
asserted. SYNC1 and SYNC2 pins are combined through an OR gate.
+3.0V to +3.6V Digital Circuit Power Supply.
This is the supply for all digital circuitry.
DVDD
Digital Circuit Ground.
GND reference point for the digital part of the AS1160.
DGND
+3.0V to +3.6V Analog Power Supply
(PLL and Analog Circuits). AVDD and DVDD
should be at the same potential and must not be more than 0.3V apart even on
AVDD
transient basis. Both supplys should be decoupled by a capacitor of typically 10nF.
Analog Ground
(PLL and Analog Circuits).
AGND
IEEE 1149.1 Test Data Input
TDI
IEEE 1149.1 Test Data Output
TDO
IEEE 1149.1 Test Mode Select Input
TMS
IEEE 1149.1 Test Clock Input
TCK
IEEE 1149.1 Test Reset Input
TRSTN
No Connection.
Leave open-circuit, do not connect these pins.
N/C
Revision 1.01
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Pin Name
See
AMSCO [ AUSTRIAMICROSYSTEMS AG ]
