AS1123
Datasheet ꢀ Detailed Description
Figure 17. Switching into Low-Current Diagnostic Mode Timing Diagram
Low-Current
Diagnosis Mode
OEN
tTESTING
Load Internal all 1s
tSU(ERROR)
LD
Test Pattern
(optional)
tGSW(ERROR)
tH(L)
CLK
tGSW(ERROR)
tSW(ERROR)
SDI
Re-entering Error Detection
Mode
(see Figure 15 on page 13)
(see Figure 16 on page 14)
Don’t
Care
TFLAG
OFLAG SFLAG
SDO
Normal Operation Current
tP1
For detailed timing information see Timing Diagrams on page 8.
V
THH Level
Two different threshold levels of the error detection can be set via a bit. The bit can be entered via 4 clock pulses during errorꢀdetection mode. To
set level 2 (VTHH is 80% of Vdd) a 0 must be placed at SDI after the rising edge of the 3rd clock pulse.
To set level 1 (VTHH is 54% of Vdd) a 1 must be placed at SDI after the 3rd clock pulse. The level 1/level 2 information will be latched through if
multiple AS1123 devices are in a chain. At the rising edge of the 4th clock pulse the bit will be read out and the AS1123 is set to Level1 or Level2.
Figure 18. VTHH Level Timing Diagram
OEN
tSU(ERROR)
LD
CLK
1 = Level1
0 = Levle2
SDI
1 = Level1
0 = Level2
SDO
TFLAG
OFLAG
SFLAG
tP4
tSU(D)
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