AS3525-A/-B C22O22
Data Sheet, Confidential
7.2.6.4 IDE Interface Registers
Table 16 IDE Interface Registers
Register Name
IdeReg_BMICP
Base Address
Offset
Note
AS3525_CF_IDE_BASE
AS3525_CF_IDE_BASE
AS3525_CF_IDE_BASE
AS3525_CF_IDE_BASE
AS3525_CF_IDE_BASE
AS3525_CF_IDE_BASE
AS3525_CF_IDE_BASE
AS3525_CF_IDE_BASE
AS3525_CF_IDE_BASE
AS3525_CF_IDE_BASE
AS3525_CF_IDE_BASE
AS3525_CF_IDE_BASE
AS3525_CF_IDE_BASE
AS3525_CF_IDE_BASE
AS3525_CF_IDE_BASE
AS3525_CF_IDE_BASE
AS3525_CF_IDE_BASE
AS3525_CF_IDE_BASE
AS3525_CF_IDE_BASE
AS3525_CF_IDE_BASE
AS3525_CF_IDE_BASE
AS3525_CF_IDE_BASE
AS3525_CF_IDE_BASE
AS3525_CF_IDE_BASE
AS3525_CF_IDE_BASE
AS3525_CF_IDE_BASE
AS3525_CF_IDE_BASE
AS3525_CF_IDE_BASE
AS3525_CF_IDE_BASE
AS3525_CF_IDE_BASE
AS3525_CF_IDE_BASE
AS3525_CF_IDE_BASE
AS3525_CF_IDE_BASE
AS3525_CF_IDE_BASE
AS3525_CF_IDE_BASE
0x00
0x02
0x04
0x06
0x40
0x41
0x42
0x43
0x44
0x45
0x46
0x47
0x48
0x4A
0x4B
0x50
0x54
0x58
0x5C
0x60
0x64
0x68
0x6C
0x70
0x74
0x78
0x7C
0x1F0
0x1F1
0x1F2
0x1F3
0x1F4
0x1F5
0x1F6
0x1F7
0x3F6
0x3F7
primary channel bus master command
primary channel bus master status
primary channel bus master table pointer
IdeReg_BMISP
IdeReg_BMIDTPP_LO
IdeReg_BMIDTPP_HI
IdeReg_IDETIMP_LO
IdeReg_IDETIMP_HI
IdeReg_IDETIMS_LO
IdeReg_IDETIMS_HI
IdeReg_SIDETIM
primary channel timing register
secondary channel timing register
slave IDE timing register
slew rate control register
IdeReg_SLEWCTL_LO
IdeReg_SLEWCTL_HI
IdeReg_IDESTAT
IDE status register
IdeReg_UDMACTL
IdeReg_UDMATIM_LO
IdeReg_UDMATIM_HI
IdeReg_MISCCTL
ultra DMA control register
ultra DMA timing register
miscellaneous control register
IdeReg_REGSTB
task file register strobe timing register
task file register recovery timing register
data register PIO strobe timing register
data register PIO recovery timing register
DMA strobe timing register
IdeReg_REGRCVR
IdeReg_DATSTB
IdeReg_DATRCVR
IdeReg_DMASTB
IdeReg_DMARCVR
IdeReg_UDMASTB
IdeReg_UDMATRP
IdeReg_UDMATENV
IdeReg_IORDYTMP
IdeReg_IORDYTMS
IdeTaskF_DATA
DMA recovery timing register
ultra DMA strobe timing register
ultra DMA ready-to-stop timing register
ultra DMA timing envelope register
primary IO ready timer configuration reg
secondary IO ready timer configuration reg
IdeTaskF_ERR_FEAT
IdeTaskF_SECT_CNT
IdeTaskF_SECT_NUM
IdeTaskF_CYL_LO
IdeTaskF_CYL_HI
IdeTaskF_DEV_HEAD
IdeTaskF_STAT_CMD
IdeTaskF_ALT_STAT_DEV_CTRL AS3525_CF_IDE_BASE
IdeTaskF_DEV_ADDR AS3525_CF_IDE_BASE
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