AS3525-A/-B C22O22
Data Sheet, Confidential
7.2.6 IDE Interface
Note: The IDE interface is only available on AS3525-A, not for AS3525-B because some of the IDE PINs are not bonded
within the AS3525-B package variant.
The IDE host interface core provides an efficient and easy-to-use interface to IDE and ATAPI devices. The core
implements programmable I/O, Multi-word DMA, and Ultra ATA-33, -66, -100 and -133 modes of operation and supports
up to two devices. The core interface to the system-on-chip provides PIO access and DMA capability to optimise data
transfers to and from the IDE devices. For ease of integration, this interface includes a register set compatible with the
Intel chip set, including a descriptor-based scatter-gather DMA core. This core is compatible with ATA-4 with Ultra ATA-
33, -66, -100 and -133 extensions. Single-word DMA is not supported.
The licensed SpeedSelectTM technology allows the core to be reconfigured to support any timing mode for PIO, Multi-
Word DMA, and Ultra ATA transfers (-33, -66, -100 or -133) while running at any clock frequency. Interface to the host
processor is the AMBA AHB bus architecture.
There are two AHB interfaces on the core: an AHB master and an AHB slave.
7.2.6.1 AHB Master Interface
The AHB Master implements a subset of the AHB protocol. The following features are supported:
•
Single transfer, unspecified-length, 4-beat incrementing and optionally 8-beat incrementing bursts (HBURST will be
‘000’, ‘001’, ‘011’, or optionally ‘101’)
•
•
•
•
•
•
•
Accesses that cross a 1kB boundary will be unspecified-length incrementing (HBURST will be ‘001’)
16-bit and 32-bit transfers only (HSIZE will only be ‘001’ or ‘010’)
BUSY cycles are not issued (HTRANS will not be ‘01’)
HPROT is not implemented
OKAY, SPLIT and RETRY responses accepted (HRESP may be ‘00’, ‘10’ or ’11’)
HLOCK asserted during fixed-length bursts
The AHB master may be granted by default
7.2.6.2 AHB Slave Interface
The AHB Slave implements a subset of the AHB protocol. The following features are supported:
•
•
•
Non-burst only (HBURST must be ‘000’)
8-, 16-, or 32-bit transfers only (HSIZE must be ‘000’, ‘001’ or ‘010’)
No advantage is gained by issuing a SEQ cycle over a NONSEQ cycle (HTRANS values of ‘10’ and ‘11’ are
interpreted identically)
•
•
•
•
HPROT is ignored
HRESP is ‘00’ (OKAY)
HREADY is issued no sooner than 2 clock cycles after a valid SEQ or NONSEQ cycle
The AHB slave may be selected by default
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