AS3525-A/-B C22O22
Data Sheet, Confidential
7.2.4 SMDMAC - Single master DMAC
The ARM PrimeCell™ PL081 “SMDMAC single master DMA controller” is included in the AHB system.
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AMBA specification Rev 2.0 compliant
two DMA channels. Each channel can support a unidirectional transfer
provides 16 peripheral DMA request lines
single DMA and burst DMA request signals. Each peripheral connected to the PrimeCell™ SMDMAC can assert either a
burst DMA request or a single DMA request. The DMA burst size is set by programming the PrimeCell™ SMDMAC
Memory-to-Memory, memory-to-peripheral, peripheral-to-memory and peripheral-to-peripheral transfers.
Scatter or gather DMA is supported through the use of linked lists. This means that the source and destination areas do not
need to occupy contiguous areas of memory
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Hardware DMA channel priority. Each DMA channel has a specific hardware priority. DMA channel 0 has the highest
priority and channel 1 has the lowest priority. If requests from two channels become active at the same time the channel
with the highest priority is serviced first.
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AHB slave DMA programming interface. The PrimeCell™ SMDMAC is programmed by writing to the DMA control registers
over the AHB slave interface
One AHB bus master for transferring data. This interface is used to transfer data when a DMA request goes active.
Figure 9 SMDMAC Block Diagram
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