AS3525-A/-B C22O22
Data Sheet, Confidential
7.2 AHB Peripheral Blocks
ARM AHB ("advanced high-performance bus") is the new generation of AMBA bus, which is intended to address the requirements of high-
performance synthesizable designs. AMBA AHB implements the features required for high performance, high clock frequency systems including:
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burst transfers
split transactions
single cycle bus master handover
non-tristate implementation
32 bit bus width
the clock frequency of the AHB can set by software up to 65MHz
7.2.1 2.5 MBIT RAM Main Memory
The memory subsystem consists of a RAM part and a ROM part.
Within the RAM memory subsystem, following functions are included:
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1-TRAM controller with AHB bus slave interface
1-TRAM memory macros
7.2.1.1 1-TRAM Controller
The 1T RAM Controller is a slave interface connected to the AMBA AHB bus.
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slave AHB interface
supports byte(8 bit), half-word(16 bit) and word(32 bit) read/write accesses
128-bit Line Buffer as temporary storage to reduce the number of memory accesses and optimise power
consumption
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controls 5TSMC 1T-RAM instances
7.2.1.2 On-Chip 1T-RAM macro blocks
TSMC Emb1tRAM™ technology is a special kind of DRAM, which is implemented in a logic CMOS process. This innovative concept and design
guarantees lowest power, high density, high performance and high yield advantages.
ECC (Error Correction Code) technique is applied in the macro to dynamically correct errors caused by hard defects or soft errors. No fuses are
needed because the conventional redundancy scheme is replaced with ECC design in the macro.
The macro can be operated at clock rate from 20 MHz up to maximum AHB bus clock frequency in flow through random access mode. In the
product, one idle cycle for refresh is needed in every 32 clock cycles.
Total 5 macros with organisation of 4Kx128 = 64 KByte each are implemented. For the refresh, one master macro is generating the refresh clock
(T1F4Kx128_PIFE) and four macros are connected serially in slave mode to the refresh clock (T1F4Kx128PIFES).
Features
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20 Mhz to 65 Mhz operation speed
Flow through random access
Built-in error correction (ECC)
128-bit wide data bus
Separated data in/out bus
SRAM-style interface operation
Built-in refresh controller with refresh clock generator
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