AS3525-A/-B C22O22
Data Sheet, Confidential
By using a five-stage pipeline, the ARM922T delivers a
throughput approaching one instruction per cycle.
Classes of Instructions
The ARM and Thumb instruction sets can be divided into four broad
classes of instruction:
Registers
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Data processing instructions
Load and store instructions
Branch instructions
The ARM9TDMI processor core consists of a 32-bit datapath
and associated conrol logic. This datapath contains 31 general-
purpose registers, coupled to a full shifter, Arithmetic Logic Unit,
and a multiplier. At any one time 16 registers are visible to the
user. The remainder are mode-specific replacement registers
(banked registers) used to speed up execution processing, and
make nested exceptions possible.
Coprocessor instructions
Data Processing Instructions
The data processing instructions operate on data held in general-
purpose registers. Of the two source operands, one is always a register.
The other has two basic forms:
Register 15 is the Program Counter (PC) that can be used in all
instructions to reference data relative to the current instruction.
R14 holds the return address after a subroutine call. R13 is
used (by software convention) as a stack pointer.
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An immediate value
A register value optionally shifted
If the operand is a shifted register, the shift can be an immediate value
or the value of another register. Four types of shift can be specified.
Most data processing instructions can perform a shift followed by a
logical or arithmetic operation.
Exeption Types/Modes
The ARM9TDMI core supports five types of exception, and a
privileged processing mode for each type. The types of
exceptions are:
There are two classes of multiply instructions:
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Fast interrupt (FIQ)
Normal interrupt (IRQ)
Memory aborts (used to implement memory
protection or virtual memory)
Attempted execution of an undefined instruction
Software interrupts (SWIs)
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Normal, 32 bit result
Long, 64 bi resut variants.
Both types of multiply instruction can optionally perform an accumulate
operation
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Load and Store Instructions
All exceptions have banked registers for R14 and R13. After an
exception, R14 holds the return address for exception
processing. This address is used both to return after the
exception is processed and to address the instruction that
caused the exception.
There are two main types of laod and store instructions:
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Load or store the value of a single register
Load or store multiple register values
Load and store single register instructions can transfer a 32-bit word, a
16-bit halfword, or an 8-bit byte between memory and a register. Byte
and halfword loads can be automatically zero extended or sign extended
as they are loaded. These instructions have three primary addressing
modes:
R13 is banked across exception modes to provide each
exception handler with a private stack pointer. The fast interrupt
mode also banks registers 8 to 12 so that interrupt processing
can begin without the need to save or restore these registers.
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Offset
Pre-indexed
Post-indexed
A seventh processing mode, System mode, uses the User
mode registers. System mode runs tasks that require a
privileged processor mode and enables them to invoke all
classes of exceptions.
The address is formed by adding an immediate, or register-based,
positive, or negative offset to a base register. Register-based offsets can
also be scaled with shift operations. Pre-indexed and post-indexed
addressing modes update the base registers with the base plus offset
calculation.
Status Registers
All other processor states are held in status registers. The
current operating processor status is in the Current Program
Status Register (CPSR). The CPSR holds:
As the PC is a general-purpose register, a 32-bit balue can be loaded
directly into the PC to perform a jump to any address in the 4GB
memory space.
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Four ALU flags (Negative, Zero, Carry, Overflow)
An interrupt disable bit for each of the IRQ and
FIQ interrupts
Load and store multiple instructions perform a block transfer of any
number of the general purpose registers to, or from, memory. Four
addressing modes are provided:
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A bit to indicate ARM or Thumb execution state
Five bits to encode the current processor mode
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Pre-increment addressing
Post-increment addressing
Pre-decrement addressing
Post-decrement addressing
All five exception modes also have a Saved Program Status
Register (SPSR) that holds the CPSR of the task immediately
before the exception occurred.
Conditional Execution
The base address is specified by a register value (that can be optionally
updated after the transfer). As the subroutine return address and the PC
values are in general-purpose registers, very efficient subroutine calls
can be constructed.
All ARM instructions can be executed conditionally and can
optionally update the four condition code flags (Negative, Zero,
Carry, and Overflow) according to their result. Fifteen conditions
are implemented.
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