AS3525-A/-B C22O22
Data Sheet, Confidential
8.4.1.7 D IO ST PU LSR
8.4.1.8 D IO ST PD LSR
Figure 71 Digital Schmitt Trigger Input with Pull-Up and Limited
Slew Rate Output
Figure 72 Digital Schmitt Trigger Input with Pull-Down and Limited
Slew Rate Output
Schmitt
Schmitt
C
C
I
PAD
I
PAD
8.4.1.9 D OUT LSR LV
8.4.1.10 D IO ST PD LSR LV
Figure 73 Digital Output with Limited Slew Rate (low voltage)
Figure 74 Digital Schmitt Trigger Input with Pull-Down and Limited
Slew Rate Output (low voltage)
I
PAD
Schmitt
C
I
PAD
9
Appendix
9.1 Memory MAP
ARM922T provides 32-bit address to access the peripherals and memory. With this 32-bit address ARM922T can access up to 4 Giga Bytes of
memory. Cocoa does not use the complete 4 GB address space.
Address 0x0000_0000 is mapped to internal ROM or External Memory interface based on the boot ROM selection by the external input pin
(Port C, xpc[0] = intBootSel) Pin intBootSel=1 at startup selects the internal ROM, intBootSel = 0 selects the external memory.
The address range starting at 0x0000_0000 is also mapped to internal RAM upon setting of the remap bit. This remap allows the user to select
either RAM or ROM at 0x0000_0000.
Table 163 Address Map
S.No
.
Start (Base)
Address
End Address
Actual
Peripheral
Comment
Block Size
AHB Blocks
0x0000_0000
0x0001_FFFF
0x003F_FFFF
128 KByte
4 MB
Internal ROM
Remap = 0 and
IntBootSel = 1
Remap = 0 and
IntBootSel = 0
0x0000_0000
External Memory IF
(MPMC Bank1 – Ext
Flash or Ext ROM)
Embedded 1T-RAM
Reserved
External Memory IF
(MPMC Bank1 – Ext
Flash or Ext ROM)
0x0000_0000
0x0100_0000
0x1000_0000
0x0004_FFFF
0x0FFF_FFFF
0x103F_FFFF
320 KByte
4 MB
Remap = 1
Aliased
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