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A3525BC21O22TRA 参数 Datasheet PDF下载

A3525BC21O22TRA图片预览
型号: A3525BC21O22TRA
PDF下载: 下载PDF文件 查看货源
内容描述: 先进的音频处理器系统 [Advanced Audio Processor System]
分类和应用:
文件页数/大小: 194 页 / 3286 K
品牌: AMSCO [ AMS(艾迈斯) ]
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AS3525-A/-B C22O22  
Data Sheet, Confidential  
7.4.12  
Audio Settings  
7.4.12.1 Register Description  
Table 134 AudioSet_1 Register  
Name  
Base  
Default  
0x00  
AudioSet_1  
I2C audio master  
First Audio Set Register  
This register is reset at a DVDD-POR.  
Offset: 0x14  
Bit  
Bit Name  
ADC_on  
Default  
Access  
Bit Description  
7
0
0
0
0
0
0
0
0
R/W  
0: ADC disabled  
1: ADC for recording is enabled  
0: Summing / Mixing stage is disabled (no audio output)  
1: Summing / Mixing stage is enabled  
0: DAC disabled  
6
5
4
3
2
1
0
SUM_on  
DAC_on  
LOUT_on  
LIN2_on  
LIN1_on  
MIC2_on  
MIC1_on  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
1: DAC enabled  
0: Line output disabled  
1: Line output enabled  
0: Line input 2 disabled  
1: Line input 2 enabled  
0: Line input 1 disabled  
1: Line input 1 enabled  
0: Microphone input 2 disabled  
1: Microphone input 2 enabled  
0: Microphone input 1 disabled  
1: Microphone input 1 enabled  
Table 135 AudioSet_2 Register  
Name  
Base  
Default  
0x00  
AudioSet_2  
I2C audio master  
Second Audio Set Register  
This register is reset at a DVDD-POR.  
Offset: 0x15  
Bit  
Bit Name  
BIAS_off  
Default  
Access  
Bit Description  
7
0
0
0
R/W  
0: bias enabled  
1: bias disabled, for power saving in non audio mode  
0: add dither to the DAC audio stream  
6
DITH_off  
R/W  
R/W  
R/W  
1: no dither added  
5
AGC_off  
0: automatic gain control for summing stage enabled  
1: automatic gain control for summing stage disabled  
Bias current reduction settings for DAC:  
4:3  
IBR_DAC<1:0>  
00  
00: 0%  
01: 25%  
10: 40%  
11: 50%  
2
LSP_LP  
0
R/W  
R/W  
Low power mode for speaker output:  
0: speaker output driver set for 4Ohm to 16Ohm loads  
1: speaker output driver set for 16Ohm or larger loads  
Bias current reduction settings for speaker output:  
1:0  
IBR_LSP<1:0>  
00  
00: 0%  
01: 17%  
10: 34%  
11: 50%  
© 2005-2009, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved.  
www.austriamicrosystems.com Revision 1.13  
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