AS3525-A/-B C22O22
Data Sheet, Confidential
Figure 56 I2S Timing
7.4.10.4 Power Save Options
The bias current of the DAC block can be reduced in three steps down to 50% to reduce the power consumption.
7.4.10.5 Clock Supervision
The digital audio interface automatically checks the LRCK. An interrupt can be generated when the state of the LRCK input changes. A bit in the
interrupt register represents the actual state (present or not present) of the LRCK.
7.4.10.6 Parameter
Table 128 Audio Converter Parameter
Symbol
A0
Parameter
Notes
Min
-43.43
-34.5
Typ
Max Unit
Gain
programmable gain DAC input
programmable gain ADC output
1.07
12
dB
dB
dB
dB
Gain Step-Size
1.5
Ax
Mute Attenuation
120
I2S inputs / outputs
VIL
SCLK, LRCK, SDI (30%DVDD/2)
SCLK, LRCK, SDI (70%DVDD/2)
SDO,IRQ @2mA
-
1.02
-
-
-
-
-
0.42
DVDD
0.3
V
VIH
VOL
VOH
V
V
SDO,IRQ @2mA
2.6
80
80
80
80
-
V
TSCLKH
TSCLKL
TSDSU
TSDHD
TSDOD
TLRSU
SCLK clock high time
ns
ns
ns
ns
ns
ns
ns
ns
ns
SCLK clock low time
Data set-up time
Data hold time
SDI versus rising edge of SCLK
SDI versus rising edge of SCLK
SDO versus falling edge of SCLK
LRCK versus rising edge of SCLK
LRCK versus rising edge of SCLK
MCLCK rising edge versus LRCK
LRCK
Data Output Delay
Clock set up time
Clock hold time
Clock separation time
clock Jitter
25
20
80
80
TLRHD
TS1, TS2
TJITTER
20
-20
BVDD = 3.3V, DVDD = 2.9V, TA= 25oC unless otherwise mentioned
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