AS3525-A/-B C22O22
Data Sheet, Confidential
7.4.10.7 Register Description
Table 129 Audio Converter Related Register
Name
Base
Offset
Description
Enable/disable DAC and ADC
Power save options and dither control
Interrupt settings for LRCK changes
AudioSet_1
AudioSet_2
IRQ_ENRD_1
I2C audio master
I2C audio master
I2C audio master
0x14
0x15
0x25
Table 130 DAC_R Register
Name
DAC_R
Base
Default
0x00
I2C audio master
Right DAC output Registers
Offset: 0x0E
This register is reset when the block is disabled in AudioSet1 register (0x14) or at a
DVDD-POR. The register cannot be written when the block is disabled.
Bit
Bit Name
DAR_VOL
Default
000
00000
Access
Bit Description
7:5
4:0
n/a
R/W
do not change
volume settings for right DAC output,
adjustable in 32 steps @ 1.5dB
11111: 6 dB gain
11110: 4.5 dB gain
..
00001: -39 dB gain
00000: -40.5 dB gain
Table 131 DAC_L Register
Name
DAC_L
Base
Default
0x00
I2C audio master
Left DAC output Registers
Offset: 0x0F
This register is reset when the block is disabled in AudioSet1 register (0x14) or at a
DVDD-POR. The register cannot be written when the block is disabled.
Bit
Bit Name
Default
Access
Bit Description
7
6
0
0
n/a
R/W
DAC_Mute_off
0: DAC output is set to mute
1: normal operation
5
0
n/a
4:0
DAL_VOL
00000
R/W
volume settings for left DAC output,
adjustable in 32 steps @ 1.5dB
11111: 6 dB gain
11110: 4.5 dB gain
..
00001: -39 dB gain
00000: -40.5 dB gain
© 2005-2009, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved.
www.austriamicrosystems.com Revision 1.13
145 - 194
AMSCO [ AMS(艾迈斯) ]
