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LP621024D-70LL 参数 Datasheet PDF下载

LP621024D-70LL图片预览
型号: LP621024D-70LL
PDF下载: 下载PDF文件 查看货源
内容描述: 128K ×8位CMOS SRAM [128K X 8 BIT CMOS SRAM]
分类和应用: 静态存储器
文件页数/大小: 16 页 / 186 K
品牌: AMICC [ AMIC TECHNOLOGY ]
 浏览型号LP621024D-70LL的Datasheet PDF文件第5页浏览型号LP621024D-70LL的Datasheet PDF文件第6页浏览型号LP621024D-70LL的Datasheet PDF文件第7页浏览型号LP621024D-70LL的Datasheet PDF文件第8页浏览型号LP621024D-70LL的Datasheet PDF文件第10页浏览型号LP621024D-70LL的Datasheet PDF文件第11页浏览型号LP621024D-70LL的Datasheet PDF文件第12页浏览型号LP621024D-70LL的Datasheet PDF文件第13页  
LP621024D Series  
Timing Waveforms (continued)  
Write Cycle 2  
(Chip Enable Controlled)  
tWC  
Address  
3
tAW  
tWR  
5
tCW  
CE1  
CE2  
(4)  
(4)  
1
tAS  
5
tCW  
2
tWP  
WE  
tDW  
tDH  
DIN  
7
tWHZ  
DOUT  
Notes: 1. tAS is measured from the address valid to the beginning of Write.  
2. A Write occurs during the overlap (tWP) of a low CE1, a high CE2 and a low WE .  
3. tWR is measured from the earliest of CE1 or WE going high or CE2 going low to the end of the Write cycle.  
4. If the CE1 low transition or the CE2 high transition occurs simultaneously with the WE low transition or after  
the WE transition, outputs remain in a high impedance state.  
5. tCW is measured from the later of CE1 going low or CE2 going high to the end of Write.  
6. OE is continuously low. ( OE = VIL)  
7. Transition is measured ±500mV from steady state. This parameter is sampled and not 100% tested.  
(August, 2001, Version 1.0)  
9
AMIC Technology, Inc.