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LP621024D-70LL 参数 Datasheet PDF下载

LP621024D-70LL图片预览
型号: LP621024D-70LL
PDF下载: 下载PDF文件 查看货源
内容描述: 128K ×8位CMOS SRAM [128K X 8 BIT CMOS SRAM]
分类和应用: 静态存储器
文件页数/大小: 16 页 / 186 K
品牌: AMICC [ AMIC TECHNOLOGY ]
 浏览型号LP621024D-70LL的Datasheet PDF文件第1页浏览型号LP621024D-70LL的Datasheet PDF文件第2页浏览型号LP621024D-70LL的Datasheet PDF文件第3页浏览型号LP621024D-70LL的Datasheet PDF文件第4页浏览型号LP621024D-70LL的Datasheet PDF文件第6页浏览型号LP621024D-70LL的Datasheet PDF文件第7页浏览型号LP621024D-70LL的Datasheet PDF文件第8页浏览型号LP621024D-70LL的Datasheet PDF文件第9页  
LP621024D Series  
AC Characteristics (TA = 0°C to + 70°C, VCC = 5V ± 10%)  
LP621024D-55LL  
LP621024D-70LL  
Unit  
Symbol  
Parameter  
Min.  
Max.  
Min.  
Max.  
Read Cycle  
tRC  
tAA  
Read Cycle Time  
55  
-
-
70  
-
-
ns  
ns  
ns  
Address Access Time  
55  
55  
70  
70  
tACE1  
-
-
CE1  
CE2  
Chip Enable Access Time  
tACE2  
tOE  
-
-
55  
30  
-
-
-
70  
35  
-
ns  
ns  
ns  
Output Enable to Output Valid  
Chip Enable to Output in Low Z  
tCLZ1  
10  
10  
CE1  
CE2  
tCLZ2  
tOLZ  
10  
5
-
-
10  
5
-
-
ns  
ns  
ns  
Output Enable to Output in Low Z  
Chip Disable to Output in High Z  
tCHZ1  
0
20  
0
25  
CE1  
CE2  
tCHZ2  
tOHZ  
tOH  
0
0
5
20  
20  
-
0
0
5
25  
25  
-
ns  
ns  
ns  
Output Disable to Output in High Z  
Output Hold from Address Change  
Write Cycle  
tWC  
Write Cycle Time  
55  
50  
0
-
-
70  
60  
0
-
-
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tCW  
Chip Enable to End of Write  
Address Setup Time  
tAS  
-
-
tAW  
Address Valid to End of Write  
Write Pulse Width  
50  
40  
0
-
60  
50  
0
-
tWP  
-
-
tWR  
Write Recovery Time  
-
-
tWHZ  
tDW  
Write to Output in High Z  
Data to Write Time Overlap  
Data Hold from Write Time  
Output Active from End of Write  
0
25  
-
0
30  
-
25  
0
30  
0
tDH  
-
-
tOW  
5
-
5
-
Notes: tCHZ1, tCHZ2, tOHZ, and tWHZ are defined as the time at which the outputs achieve the open circuit condition and are  
not referred to output voltage levels.  
(August, 2001, Version 1.0)  
5
AMIC Technology, Inc.