LP621024D Series
128K X 8 BIT CMOS SRAM
Features
n Single +5V power supply
n Common I/O using three-state output
n Access times: 55/70 ns (max.)
n Current:
n Output enable and two chip enable inputs for easy
application
Very low power version: Operating: 70mA (max.)
n Data retention voltage: 2V (min.)
n Available in 32-pin DIP, SOP TSOP and TSSOP
(8 X 13.4mm) packages
Standby:
25mA (max.)
n Full static operation, no clock or refreshing required
n All inputs and outputs are directly TTL-compatible
General Description
The LP621024D is a low operating current 1,048,576-bit
static random access memory organized as 131,072
words by 8 bits and operates on a single 5V power
supply.
Inputs and three-state outputs are TTL compatible and
allow for direct interfacing with common system bus
structures.
Two chip enable inputs are provided for POWER-DOWN
and device enable and an output enable input is included
for easy interfacing.
Data retention is guaranteed at a power supply voltage
as low as 2V.
Pin Configurations
n DIP
n SOP
n TSOP/(TSSOP)
1
VCC
A15
CE2
1
VCC
A15
CE2
32
31
30
32
31
30
NC
A16
A14
NC
16
A16
A14
1
2
3
4
5
6
2
3
4
5
6
WE
A13
A8
WE
A13
A8
A12
A7
A6
A5
A4
A3
A2
A12
A7
A6
A5
A4
A3
A2
29
28
27
26
29
28
27
26
A9
A9
7
8
7
8
A11
A11
25
24
23
22
25
24
23
22
OE
OE
9
9
A10
A10
10
11
12
13
14
15
16
10
11
12
13
14
15
16
CE1
CE1
A1
A0
A1
A0
I/O8
I/O8
21
20
19
18
17
21
20
19
18
17
I/O1
I/O2
I/O1
I/O2
I/O7
I/O6
I/O5
I/O4
I/O7
I/O6
I/O5
I/O4
I/O3
I/O3
32
17
GND
GND
Pin No.
1
2
3
4
5
6
7
8
9
10
A16
26
11
12
A12
28
13
A7
14
A6
15
A5
16
A4
32
Pin
Name
A11
17
A9
18
A2
A8
19
A1
A13
20
WE
21
CE2
22
A15
VCC
24
NC
25
A14
27
Pin No.
23
29
30
31
Pin
Name
I/O3
I/O8
A3
A0
I/O1
I/O2
GND
I/O4
I/O5
I/O6
I/O7
CE1
A10
OE
(August, 2001, Version 1.0)
1
AMIC Technology, Inc.
AMICC [ AMIC TECHNOLOGY ]
