A625308A Series
Timing Waveforms (continued)
Read Cycle 3 (1, 3, 4)
CE
tACE
5
tCLZ
5
tCHZ
DOUT
Notes: 1. WE is high for Read Cycle.
2. Device is continuously enabled, CE = VIL.
3. Address valid prior to or coincident with CE transition low.
4. OE = VIL.
5. Transition is measured ±500mV from steady state. This parameter is sampled and not 100% tested.
Write Cycle 1 (6)
(Write Enable Controlled)
tWC
Address
3
tAW
tWR
5
tCW
CE
WE
DIN
(4)
1
2
tAS
tWP
tDW
tDH
7
tWHZ
7
tOW
DOUT
PRELIMINARY
(July, 2002, Version 0.2)
7
AMIC Technology, Inc.