A625308A Series
Timing Waveforms (continued)
Write Cycle 2 (6)
(Chip Enable Controlled)
tWC
Address
3
tAW
tWR
5
tCW
CE
(4)
1
tAS
2
tWP
WE
tDW
tDH
DIN
7
tWHZ
DOUT
Notes: 1. tAS is measured from the address valid to the beginning of Write.
2. A Write occurs during the overlap (tWP) of a low CE and a low WE .
3. tWR is measured form the earliest of CE or WE going high to the end of the Write cycle.
4. If the CE low transition occurs simultaneously with the WE low transition or after the WE transition, outputs
remain in a high impedance state.
5. tCW is measured from the later of CE going low to the end of Write.
6. OE level is high or low.
7. Transition is measured ±500mV from steady. This parameter is sampled and not 100% tested.
PRELIMINARY
(July, 2002, Version 0.2)
8
AMIC Technology, Inc.
AMICC [ AMIC TECHNOLOGY ]
