A43L2616B
Write Interrupted by Precharge Command & Write Burst Stop Cycle @ Burst Length = Full Page
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CLOCK
CKE
High
CS
RAS
CAS
RAa
CAa
CAb
ADDR
BA0
BA1
A10/AP
RAa
tRDL
tBDL
* Note 2
WE
DQM
DQ
DAa0 DAa1 DAa2 DAa3 DAa4
DAb0 DAb1 DAb2 DAb3 DAb4 DAb5
Write
(A-Bank)
Write
(A-Bank)
Precharge
(A-Bank)
Row Active
(A-Bank)
Burst Stop
: Don't care
* Note : 1. At full page mode, burst is wrap-around at the end of burst. So auto precharge is impossible.
2. Data-in at the cycle of interrupted by precharge cannot be written into the corresponding memory cell.
It is defined by AC parameter of tRDL(=2CLK).
DQM at write interrupted by precharge command is needed to prevent invalid write.
DQM should mask invalid input data on precharge command cycle when asserting precharge before end of burst.
Input data after Row precharge cycle will be masked internally.
3. Burst stop is valid at every burst length.
(December, 2009, Version 1.3)
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AMIC Technology, Corp.
AMICC [ AMIC TECHNOLOGY ]
