A43L8316
Read & Write Cycle at Different Bank @Burst Length=4
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CLOCK
CKE
High
CS
RAS
CAS
RAa
CAa
RBb
CBb
RAc
CAc
ADDR
BA
A8/AP
RAa
RBb
RAc
tCDL
*Note 1
WE
DQM
DQ
(CL=2)
QAa0 QAa1 QAa2 QAa3
DBb0 DBb1 DBb2 DBb3
DBb0 DBb1 DBb2 DBb3
QAc0 QAc1 QAc2
QAc0 QAc1
DQ
(CL=3)
QAa0 QAa1 QAa2 QAa3
Row Active
(A-Bank)
Read
(A-Bank)
Precharge
(A-Bank)
Write
(B-Bank)
Read
(A-Bank)
Row Active
(B-Bank)
Row Active
(A-Bank)
: Don't care
* Note : tCDL should be met to complete write.
Preliminary (April, 2000, Version 1.0)
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AMIC Technology, Inc.