A43L8316
Page Read & Write Cycle at Same Bank @Burst Length=4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLOCK
CKE
High
CS
tRCD
RAS
CAS
*Note 2
ADDR
Ra
Ca0
Cb0
Cc0
Cd0
BA
A8/AP
Ra
tRDL
tCDL
WE
*Note 2
*Note1
*Note3
DQM
DQ
(CL=2)
Qa0 Qa1 Qb0
Qb1
Dc0
Dc1
Dc1
Dd0
Dd0
Dd1
Dd1
DQ
(CL=3)
Qa0 Qa1 Qb0
Dc0
Row Active
(A-Bank)
Write
(A-Bank)
Write
(A-Bank)
Read
(A-Bank)
Read
(A-Bank)
Precharge
(A-Bank)
: Don't care
*Note : 1. To write data before burst read ends, DQM should be asserted three cycle prior to write
command to avoid bus contention.
2. Row precharge will interrupt writing. Last data input, tRDL before Row precharge, will be written.
3. DQM should mask invalid input data on precharge command cycle when asserting precharge
before end of burst. Input data after Row precharge cycle will be masked internally.
Preliminary (April, 2000, Version 1.0)
26
AMIC Technology, Inc.
AMICC [ AMIC TECHNOLOGY ]
