A43L8316
Page Write Cycle at Different Bank @Burst Length=4
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CLOCK
CKE
High
CS
RAS
CAS
*Note 2
RAa
RAa
CAa
RBb
RBb
CBb
CAc
CBd
ADDR
BA
A8/AP
DQ
DAa0 DAa1 DAa2 DAa3 DBb0 DBb1 DBb2 DBb3 DAc0 DAc1 DBd0 DBd1
tCDL
tRDL
WE
*Note 1
DQM
Row Active
(B-Bank)
Write
(B-Bank)
Precharge
(Both Banks)
Write
(A-Bank)
Row Active with
(A-Bank)
Write
(A-Bank)
Write
(B-Bank)
: Don't care
* Note:
1. To interrupt burst write by Row precharge, DQM should be asserted to mask invalid input data.
2. To interrupt burst write by Row precharge, both the write and precharge banks must be the same.
Preliminary (April, 2000, Version 1.0)
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AMIC Technology, Inc.
AMICC [ AMIC TECHNOLOGY ]
