A43L8316
5. Write Interrupted by Precharge & DQM
CLK
Note 2
Note 1
CMD
WR
D0
PRE
D3
DQM
DQ
D1
D2
Masked by DQM
Note : 1. To inhibit invalid write, DQM should be issued.
2. This precharge command and burst write command should be of the same bank, otherwise it is not precharge
interrupt but only another bank precharge of dual banks operation.
6. Precharge
1) Normal Write (BL=4)
CLK
CMD
DQ
WR
D0
PRE
D1
D2
D3
tRDL
Note 1
2) Read (BL=4)
CLK
Note 2
CMD
RD
PRE
Q2
1
DQ(CL2)
Q0
Q1
Q0
Q3
Q2
2
DQ(CL3)
Q1
Q3
7. Auto Precharge
1) Normal Write (BL=4)
CLK
CMD
DQ
WR
D0
D1
D2
D3
Note 2
Auto Precharge Starts
2) Read (BL=4)
CLK
CMD
DQ(CL2)
DQ(CL3)
RD
Q0
Q1
Q0
Q2
Q1
Q3
Q2
Q3
Note 2
Auto Precharge Starts
* Note : 1. Number of valid output data after Row Precharge : 1,2 for CAS Latency = 2,3 respectively.
2. The row active command of the precharge bank can be issued after tRP from this point.
The new read/write command of other active bank can be issued from this point.
At burst read/write with auto precharge,
interrupt of the same/another bank is illegal.
CAS
Preliminary (April, 2000, Version 1.0)
18
AMIC Technology, Inc.
AMICC [ AMIC TECHNOLOGY ]
