A43E26161
8. Burst Stop & Interrupted by Precharge
1) Normal Write (BL=4)
CLK
2) Write Burst Stop (BL=8)
CLK
CMD
CMD
WR
PRE
WR
STOP
DQM
DQ
DQM
DQ
D0
D1
D2
D3
D0
D1
D2
D3
D4
D5
tRDL Note 1
t
BDL Note 2
1) Read Interrupted by Precharge (BL=4)
CLK
4) Read Burst Stop (BL=4)
CLK
CMD
CMD
RD
PRE
Q0
RD
STOP
Q0
Note 3
1
1
DQ(CL2)
DQ(CL3)
Q1
Q0
DQ(CL2)
DQ(CL3)
Q1
Q0
2
2
Q1
Q1
9. MRS
Mode Register Set
CLK
Note 1
PRE
MRS
ACT
CMD
t
RP
2CLK
Note : 1. tRDL: 1CLK
2. tBDL: 1CLK; Last data in to burst stop delay.
Read or write burst stop command is valid at every burst length.
3. Number of valid output data after row precharge or burst stop: 1,2 for CAS latency = 2, 3 respectively.
4. PRE: All banks precharge if necessary.
MRS can be issued only when all banks are in precharged state.
(December, 2004, Version 1.0)
18
AMIC Technology, Corp.
AMICC [ AMIC TECHNOLOGY ]
