A43E26161
3. CAS Interrupt (I)
1) Read interrupted by Read (BL=4)Note 1
CLK
CMD
RD
A
RD
B
ADD
DQ(CL2)
DQ(CL3)
QA0 QB0 QB1 QB2 QB3
QA0 QB0 QB1 QB2 QB3
t
CCD
Note2
2) Write interrupted by Write (BL =2)
3) Write interrupted by Read (BL =2)
CLK
WR WR
WR
RD
CMD
t
CCD
tCCD
Note2
Note2
ADD
DQ
A
B
A
B
DA0 DB0 DB1
DQ(CL2)
DQ(CL3)
DA0
QB0 QB1
t
CDL
Note3
DA0
QB0 QB1
t
CDL
Note3
Note : 1. By “Interrupt”, It is possible to stop burst read/write by external command before the end of burst.
By “ Interrupt”, to stop burst read/write by access; read, write and block write.
CAS
2. tCCD :
CAS
to
delay. (=1CLK)
CAS
CAS
3. tCDL : Last data in to new column address delay. (= 1CLK).
(December, 2004, Version 1.0)
15
AMIC Technology, Corp.
AMICC [ AMIC TECHNOLOGY ]
