A25L80P
Read Data Bytes at Higher Speed (FAST_READ)
instruction. When the highest address is reached, the address
counter rolls over to 000000h, allowing the read sequence to
be continued indefinitely.
S
The device is first selected by driving Chip Select ( ) Low. The
instruction code for the Read Data Bytes at Higher Speed
(FAST_READ) instruction is followed by a 3-byte address
(A23-A0) and a dummy byte, each bit being latched-in during
the rising edge of Serial Clock (C). Then the memory contents,
at that address, is shifted out on Serial Data Output (Q), each
bit being shifted out, at a maximum frequency fC, during the
falling edge of Serial Clock (C).
The instruction sequence is shown in Figure 9. The first byte
addressed can be at any location. The address is automatically
incremented to the next higher address after each byte of data
is shifted out. The whole memory can, therefore, be read with a
single Read Data Bytes at Higher Speed (FAST_READ)
The Read Data Bytes at Higher Speed (FAST_READ)
S
instruction is terminated by driving Chip Select ( ) High. Chip
S
Select ( ) can be driven High at any time during data output.
Any Read Data Bytes at Higher Speed (FAST_READ) in-
struction, while an Erase, Program or Write cycle is in progress,
is rejected without having any effects on the cycle that is in
progress.
Figure 9. Read Data Bytes at Higher Speed (FAST_READ) Instruction Sequence and Data-Out Sequence
S
6
0
1
2
3
4
5
7
8
9 10
28 29 30 31
C
D
Q
Instruction
24-Bit Address
21
23
2
1
0
22
3
MSB
High Impedance
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C
32 33 34 35 36 37 38 39 40
Dummy Byte
41 42 43 44 45 46 47
7
6
5
4
3
2
0
1
D
Q
Data Out 2
Data Out 1
0
5
4
1
5
4
1
6
3
2
0
6
3
2
7
7
7
MSB
MSB
MSB
Note: Address bits A23 to A20 are Don’t Care.
PRELIMINARY (May 2005, Version 0.0)
14
AMIC Technology Corp.
AMICC [ AMIC TECHNOLOGY ]
