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A25L40PMF-50U 参数 Datasheet PDF下载

A25L40PMF-50U图片预览
型号: A25L40PMF-50U
PDF下载: 下载PDF文件 查看货源
内容描述: 8兆位,低电压,串行闪存,具有50 MHz SPI总线接口 [8 Mbit, Low Voltage, Serial Flash Memory With 50 MHz SPI Bus Interface]
分类和应用: 闪存
文件页数/大小: 34 页 / 514 K
品牌: AMICC [ AMIC TECHNOLOGY ]
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A25L80P  
Read Data Bytes (READ)  
single Read Data Bytes (READ) instruction. When the highest  
address is reached, the address counter rolls over to 000000h,  
allowing the read sequence to be continued indefinitely.  
S
The device is first selected by driving Chip Select ( ) Low. The  
instruction code for the Read Data Bytes (READ) instruction is  
followed by a 3-byte address (A23-A0), each bit being  
latched-in during the rising edge of Serial Clock (C). Then the  
memory contents, at that address, is shifted out on Serial Data  
Output (Q), each bit being shifted out, at a maximum frequency  
fR, during the falling edge of Serial Clock (C).  
The Read Data Bytes (READ) instruction is terminated by  
S
S
driving Chip Select ( ) High. Chip Select ( ) can be driven  
High at any time during data output. Any Read Data Bytes  
(READ) instruction, while an Erase, Program or Write cycle is  
in progress, is rejected without having any effects on the cycle  
that is in progress.  
The instruction sequence is shown in Figure 8. The first byte  
addressed can be at any location. The address is automatically  
incremented to the next higher address after each byte of data  
is shifted out. The whole memory can, therefore, be read with a  
Figure 8. Read Data Bytes (READ) Instruction Sequence and Data-Out Sequence  
S
6
0
1
2
3
4
5
7
8
9 10  
28 29 30 31 32 33 34 35 36 37 38 39  
C
D
Q
Instruction  
24-Bit Address  
23  
21  
2
1
0
22  
3
MSB  
Data Out 2  
Data Out 1  
High Impedance  
5
4
1
0
6
3
2
7
7
MSB  
PRELIMINARY (May 2005, Version 0.0)  
13  
AMIC Technology Corp.  
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