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AMIS-710651 参数 Datasheet PDF下载

AMIS-710651图片预览
型号: AMIS-710651
PDF下载: 下载PDF文件 查看货源
内容描述: 彩色CIS模组 [Color CIS Module]
分类和应用:
文件页数/大小: 9 页 / 365 K
品牌: AMI [ AMI SEMICONDUCTOR ]
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AMIS-710651-A4: Color CIS Module
5.0 Physical Overview
Table 2: Physical Overview
Parameter
Image sensors
Module outside dimension
Circuit power supply
Data output
Data Sheet
Specification
A<OS-720058
≅12.3mm
x 18.9mm x 232mm
Typical 3.3V @ 70mA
One analog output
Note
See image sensor data sheet
6.0 Recommended Operating Conditions
All tests were conducted at the typical pixel rate of 3.0MHz
Table 3: Recommended Operating Conditions (25 C)
Parameter
Symbol
Power supply
VDD
IDD
(1)
Video output level
VP
(2)
Reference voltage input
VREF
Input voltage for digital high (input clocks, SP
VIH
and CP)
Input voltage for digital low (input clocks SS
VIL
and CP)
(3)
Clock frequency
FREQ
(3)
Pixel frequency
PRATE
(4)
Clock pulse high duty cycle
DUTY
Clock pulse high duration
TPW
(5)
Integration time
TINT
(6)
Operating temperature
TOP
Notes:
(1)
(2)
(3)
(4)
(5)
°
Min.
0.15
3.2
0
0.50
0.50
200
~1300
Typ.
3.3
70
0.2
1.2
VDD
Max.
100
VDD +0.3
0.8
Units
V
mA
V
V
V
V
MHz
MHz
%
ns
µs
°
C
3.0
3.0
50
4.0
4.0
25
10000
50
(6)
VP represents the average value Vp(n) for all n in line scans, where n is the sequential number of a pixel. This signal pixel level should be operated at less than
saturation levels, i.e., <1.3V.
VREF is used to adjust the video output bias. Under normal operation it is left unconnected.
FREQ is the input clock (CP) frequency and the pixel rate (PRATE). The minimum rate for FREQ and PRATE should be consistent with the maximum TINT, see
Note (5).
DUTY is the ratio of the clock’s pulse width to its pulse period.
TINT is the time interval between two start pulses (SP). Hence, if SP is generated from a clock count down circuit, it will be directly proportional to the clock
frequency. There must be a minimum of (56+1204) clock cycles between the two SPs. The longest integration time is determined by the degree of leakage current
degradation that can be tolerated by the system. A 10ms maximum is a typical rule-of-thumb. An experienced CIS user can use his discretion to determine the
desired leakage tolerance level for the given system.
TOP is a conservative engineering estimate. It is based on measurements of similar CIS modules. In production, they are measured under standard QA practices,
that is, under the control of ISO 9000 standards.
AMI Semiconductor
– Aug. 06, M-20609-001
www.amis.com
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