AMIS-710651-A4: Color CIS Module
Data Sheet
50%
50%
CLK
TS
90%
VOUT
Prt
1 Pixel
Figure 5: Pixel Timing
Table 6: Clock Timing Characteristics for Timing Diagrams
Parameter
Symbol
Min.
Clock cycle time
CLKp
250
Clock pulse width
CLKpw
Clock duty cycle
Prohibit crossing time SP
tprh
30
Data setup time
Tset
20
Data hold time
Thold
25
Signal delay time
tdl
Signal settling time
Signal fall time
Notes:
(1)
(2)
Typ.
250
125
50
Max.
2000
50
130
60
Units
ns
ns
%
ns
ns
ns
ns
ns
ns
tst
tsigf
All of the symbol definitions used in Table 6 are shown in the figures in Section 9.0. The clocks, CP and SP are compatible with CMOS clock drivers.
Maximum clock cycle time, as with minimum FREQ, must be consistent with maximum TINT. See Table 3, Note 3.
10.0 Maximum Ratings
Table 7: Maximum Ratings (Not to be Used for Continuous Operation)
Parameter
Symbol
Power supply voltage
VDD
Input voltage
VIN
Ambient temperature
TA (PCB surface)
Ambient humidity
Maximum operating case temperature
HA
PCB temperature
Specification
3.3V
VDD
°
0 to 50 C
°
-10 to +75 C
0 to 80%
°
70 C
Note
SP & CP
Operational storage
Non-condensing
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– Aug. 06, M-20609-001
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