AMIS-710627-A4, AMIS-710628-A4, AMIS-710629-A4:
Data Sheet
600dpi CIS Modules
11.0 Timing Characteristics at 25°C
The timing characteristics at 25°C for the I/O clocks are shown in Figure 5 and their definitions detailed in Table 12. Only one video
output is shown because all four video sections have identical electrical characteristics. Since there are seven die in sections one, two
and three and six die in Section 4, the output waveform for Section 4 (Vout 4) is shorter by 192 pixels.
Figure 5: Module Timing Diagram
Table 12: Timing Definitions
Item
Clock cycle time
Symbol
Min.
0.182
46
25
50
50
50
50
100
Typ.
Max.
1.93
1448
75
Units
µs
ns
%
ns
ns
ns
ns
ns
to
tw
Clock pulse width
Clock duty cycle
Prohibit crossing time of the SP(1)
Data setup time
Data hold time
Signal delay time
Signal settling time
Note:
tprh
tds
tdh
tdl
tsh
1.
"Prohibit crossing of the start pulse", tprh, is to indicate that the start pulse should not be active high between two consecutive low going clock pulses. All falling
clock edges under an active high start pulse loads the internal shift register, therefore the start pulse must be active over only one falling clock edge. A high start
pulse crossing over any rising clock edges are ignored by the shift register. One simple way to ensure that the start pulse will not be actively high for any two
consecutive falling clock edges is to generate the start pulse on a rising clock edge and terminate it on the following rising clock edge.
AMI Semiconductor – Jan. 06, M-20493-001
9
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