AMIS-30624 I2C Microstepping Motordriver
Data Sheet
(2) I2C-bus compatible devices must reset their bus logic on receipt of a START condition such that they all anticipate the sending of a slave address, even if these
START conditions are not positioned according to the proper format.
(3) A START condition immediately followed by a STOP condition (void message) is an illegal format.
16.7 7-bit Addressing
The addressing procedure for the I2C-bus is such that the first byte after the START condition usually determines which slave will be
selected by the master. The exception is the general call address which can call all devices. When this address is used all devices
should respond with an acknowledge. The second byte of the general call address then defines the action to be taken.
16.7.1. Definition of Bits in the First Byte
The first seven bits of the first byte make up the slave address. The eighth bit is the least significant bit (LSB). It determines the
direction of the message. If the LSB is a “zero” it means that the master will write information to a selected slave. A “one” in this position
means that the master will read information from the slave. When an address is sent, each device in a system compares the first seven
bits after the START condition with its address. If they match, the device considers itself addressed by the master as a slave-receiver or
slave-transmitter, depending on the R/ W bit.
LSB
R/W
MSB
SLAVE ADDRESS
Figure 33: First Byte after START Procedure
PC20070219.2
AMIS-30624 is provided with a physical address in order to discriminate this circuit from other circuits on the I2C bus. This address is
coded on seven bits (two bits being internally hardwired to ‘1’), yielding the theoretical possibility of 32 different circuits on the same
bus. It is a combination of four OTP memory bits (OTP Memory Structure) and of the externally hardwired address bits (pin HW). HW
must either be connected to ground or to Vbat. When HW is not connected and is left floating, correct functionality of the positioner is
not guaranteed. The motor will be driven to the programmed secure position (See Hardwired Address – OPEN).
LSB
R/W
MSB
1
1
PA3 PA2 PA1 PA0 HW
Hardwired Address Bit
OTP memory
PC20070219.3
Figure 34: First Byte After START Procedure
16.7.2. General Call Address
The AMIS-30624 supports also a “general call” address “000 0000”, which can address all devices. When this address is used all
devices should respond with an acknowledge. The second byte of the general call address then defines the action to be taken.
AMI Semiconductor – Apr. 2007, Rev 3.1, M-20664-003
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