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AMIS-30624PGA 参数 Datasheet PDF下载

AMIS-30624PGA图片预览
型号: AMIS-30624PGA
PDF下载: 下载PDF文件 查看货源
内容描述: I2C微Motordriver [I2C Microstepping Motordriver]
分类和应用:
文件页数/大小: 56 页 / 2356 K
品牌: AMI [ AMI SEMICONDUCTOR ]
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AMIS-30624 I2C Microstepping Motordriver  
Data Sheet  
2) If the microcontroller wants to receive information from motordriver_2:  
Microcontroller (master) addresses motordriver_2 (slave)  
Microcontroller (master-receiver) receives data from motordriver_2 (slave-transmitter)  
Microcontroller terminates the transfer  
Even in this case the master generates the timing and terminates the transfer.  
Generation of the signals on the I2C-bus is always the responsibility of the master device. It generates its own clock signal when  
transferring data on the bus. Bus clock signals from a master can only be altered when they are stretched by a slow slave device  
holding-down the clock line.  
16.3 General Characteristics  
+5 V  
Rp  
Rp  
Serial Data Line  
Serial Clock Line  
SCK  
SDA  
SCL  
SDA  
2
1
Clock IN  
Data IN  
Clock IN  
Data IN  
Clock OUT  
Data OUT  
Clock OUT  
Data OUT  
AMIS-30624  
MASTER  
PC20060925.7  
Figure 24: Connection of a Device to the I2C-bus  
Both SDA and SCK are bi-directional lines connected to a positive supply voltage via a pull-up resistor (see Figure 24). When the bus is  
free both lines are HIGH. The output stages of the devices connected to the bus must have an open drain to perform the wired-AND  
function. Data on the I2C-bus can be transferred up to 400kbits/s in fast mode. The number of interfaces connected to the bus is  
dependent on the maximum bus capacitance limit (See CB in Table 6) and the available number of addresses.  
16.4 Bit Transfer  
The levels for logic ‘0’ (LOW) and ‘1’ (HIGH) are not fixed in the I2C standard but dependent on the used VDD level. Using AMIS-30624,  
the levels are specified in Table 5. One clock pulse is generated for each data bit transferred.  
16.4.1. Data Validity  
The data on the SDA line must be stable during the HIGH period of the clock. The HIGH or LOW state of the data line can only change  
when the clock signal on the SCL line is LOW (See Figure 25).  
SDA  
SCK  
Data line stable  
-> Data valid  
Change of  
data allowed  
PC20070217.2  
Figure 25: Bit Transfer on the I2C-bus  
AMI Semiconductor – Apr. 2007, Rev 3.1, M-20664-003  
40  
www.amis.com