D A T A S H E E T
Table 8. Primary Vendor-Specific Extended Query
Addresses
Addresses
(Word Mode)
(Byte Mode)
Data
Description
40h
41h
42h
80h
82h
84h
0050h
0052h
0049h
Query-unique ASCII string “PRI”
43h
44h
86h
88h
0031h
0030h
Major version number, ASCII
Minor version number, ASCII
Address Sensitive Unlock
0 = Required, 1 = Not Required
45h
46h
47h
48h
8Ah
8Ch
8Eh
90h
0000h
0002h
0001h
0001h
Erase Suspend
0 = Not Supported, 1 = To Read Only, 2 = To Read & Write
Sector Protect
0 = Not Supported, X = Number of sectors in per group
Sector Temporary Unprotect
00 = Not Supported, 01 = Supported
Sector Protect/Unprotect scheme
49h
92h
0004h
01 = 29F040 mode, 02 = 29F016 mode,
03 = 29F400 mode, 04 = 29LV800A mode
Simultaneous Operation
00 = Not Supported, 01 = Supported
4Ah
4Bh
4Ch
94h
96h
98h
0000h
0000h
0000h
Burst Mode Type
00 = Not Supported, 01 = Supported
Page Mode Type
00 = Not Supported, 01 = 4 Word Page, 02 = 8 Word Page
Hardware Data Protection
The command sequence requirement of unlock cycles
for programming or erasing provides data protection
against inadvertent writes (refer to Table 9 for com-
mand definitions). In addition, the following hardware
data protection measures prevent accidental erasure
or programming, which might otherwise be caused by
Write Pulse “Glitch” Protection
Noise pulses of less than 5 ns (typical) on OE#, CE#
or WE# do not initiate a write cycle.
Logical Inhibit
Write cycles are inhibited by holding any one of OE# =
spurious system level signals during V
power-up
CC
V , CE# = V or WE# = V . To initiate a write cycle,
IL
IH
IH
and power-down transitions, or from system noise.
CE# and WE# must be a logical zero while OE# is a
logical one.
Low V
Write Inhibit
CC
When V
is less than V
, the device does not ac-
LKO
Power-Up Write Inhibit
CC
cept any write cycles. This protects data during V
CC
If WE# = CE# = V and OE# = V during power up,
IL
IH
power-up and power-down. The command register
and all internal program/erase circuits are disabled,
and the device resets. Subsequent writes are ignored
the device does not accept commands on the rising
edge of WE#. The internal state machine is automati-
cally reset to reading array data on power-up.
until V
is greater than V
. The system must pro-
CC
LKO
vide the proper signals to the control pins to prevent
unintentional writes when V is greater than V
.
CC
LKO
22358B7 May 5, 2006
Am29LV160D
19
AMD [ AMD ]
